Abstract: A memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. A first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. A second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. The first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.

Abstract: Disclosed is a device for processing a substrate, the device including: a support unit including a spin chuck supporting a substrate, a rotation shaft supporting the spin chuck, and a driver providing rotational force to the rotation shaft; and a determination unit for determining whether the rotation shaft is defective, in which the determination unit determines whether the rotation shaft is defective based on a current value applied to the driver while the rotation shaft is rotating.

Abstract: A display device includes: a support substrate including a main area including a display area in which light emitting areas are arranged, a hole area surrounded by the main area, and a hole peripheral area between the hole area and the main area; a circuit layer on the support substrate; an element layer on the circuit layer; a capping layer on the element layer; an encapsulation substrate on the capping layer and bonded to the support substrate; a first hole peripheral dam in the hole peripheral area and surrounding a periphery of the hole area; a second hole peripheral dam in the hole peripheral area and surrounding a periphery of the first hole peripheral dam; and an auxiliary dam in a valley area of the hole peripheral area between the first hole peripheral dam and the second hole peripheral dam.

Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.

Abstract: Provided is an organic light emitting device comprising an anode; a cathode; and a light emitting layer provided between the anode and the cathode, wherein the light emitting layer comprises a first host material comprising a compound of Chemical Formula A: a second host material including a compound of Chemical Formula B: and a dopant material comprising a compound of Chemical Formula C or D:

Abstract: Provided is a method and an apparatus for targeting an object in a game. The method of targeting an object in a game includes: setting a center point of a first targeting area based on a first input from a user; displaying the first targeting area surrounded by a closed curve around the center point on a screen of a user terminal; displaying a list including at least one object located in the first targeting area on the screen; and moving the first targeting area based on a second input by the user received after the first input.

Abstract: The present disclosure provides: a compound of a specific chemical structure, having excellent activity with respect to BTK degradation; or a pharmaceutically acceptable salt thereof. The present disclosure also provides a composition comprising the compound or pharmaceutically acceptable salts thereof. The present disclosure also provides are pharmaceutical use for treating or preventing BTK-associated diseases (for example, autoimmune diseases or cancer) of the compound, the salt thereof, and the composition comprising same according to the present disclosure. The present disclosure also provides a method for treating or preventing BTK-associated diseases (for example, autoimmune diseases or cancer), comprising administering, to a subject requiring treatment, an effective amount of the compound, the salt thereof, or the composition comprising same according to the present disclosure.

Abstract: A memory device may include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked along a first direction, an opening extending in the first direction from at least one conductive layer, among the plurality of conductive layers, in the stack structure, and a contact plug in the opening. The opening may include a protrusion portion protruding in a second direction intersecting the first direction.

Abstract: The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a subLED electrically connected to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: Provided is an ultrasonic welding system and a power module package for a power converting apparatus to which a substrate where connection members are ultrasonic welded by using the system is applied, wherein the ultrasonic welding system includes a waffle pack 110 on which connection members 10 to be ultrasonic welded onto a substrate 20 are arranged in a specific form, a centering aligning unit 120 which aligns and centers the connection members 10 transferred from the waffle pack 110, an ultrasonic welding part 130 which fixes the substrate 20 and ultrasonic welds the connection members 10 aligned by the centering aligning unit 120 onto the substrate 20, and a picker 140 which separately picks the connection members 10 from the waffle pack 110 to be transferred to the centering aligning unit 120 and re-picks the aligned connection members 10 from the centering aligning unit 120 to be transferred to ultrasonic welding positions on the substrate 20 fixed to the ultrasonic welding part 130, wherein the connec

Abstract: In an embodiment of the disclosed technology, when a virtual machine is migrated between a plurality of host devices which are allocated with and use memory regions of a data storage device, data related to the virtual machine may be migrated without using a bandwidth between the data storage device and the host devices or by minimizing use of a bandwidth.

Abstract: In an embodiment of the disclosed technology, a defective memory region is detected on the basis of operation information of a memory region included in a memory system and allocated to a host device, a warning signal is transmitted to a host device to which the defective memory region is allocated, and the defective memory region is excluded from a pool of allocatable memory regions to reduce or prevent data loss of a host device using memory regions of the memory system that may occur due to the defective memory region.

Abstract: A source driver IC capable of cancelling an output offset is provided. The source driver IC comprises a reception circuit configured to receive an input data packet from a timing controller when operating in a normal mode and obtain an image data and a first clock signal from the input data packet, a control circuit configured to receive and output the image data and the first clock signal from the reception circuit when operating in the normal mode. The control circuit is configured to receive and output a second clock signal from the timing controller when operating in a low power mode. The source driver IC further comprises an output buffer circuit configured to output a data voltage related to the image data when operating in the normal mode and maintain an output of the data voltage when operating in the low power mode.

Abstract: The present disclosure, in an aspect, relates to a source driver to control a bias current, and more particularly, to a source driver, in which a bias current of a buffer is controlled depending on a distance between the source driver and a pixel in a data line and a position, regarding which a bias current is set, and the intensity of the bias current are changed in every frame so that unnecessary power consumption due to bias currents may be reduced and a block-dim phenomenon may be alleviated.

Abstract: The present disclosure relates to a data driving device and a display device including the same, and more particularly, to a data driving device and a display device including the same, capable of improving the slew rate and the display speed of the display device by overdriving a pixel of a display panel with a power voltage of the data driving device.

Abstract: A display device includes: a substrate including an opening area, a peripheral area surrounding the opening area, and a display area surrounding the peripheral area; a transistor disposed on the display area of the substrate; a first electrode electrically connected to the transistor; an intermediate layer overlapping the first electrode; a second electrode disposed on the intermediate layer; a first dam disposed on the peripheral area of the substrate; and a first encapsulation inorganic layer disposed on the second electrode, wherein the first encapsulation inorganic layer is in contact with a side of the first dam in the peripheral area.

Abstract: A display driving device for driving a display panel, including a gate line, a data line intersecting with the gate line, and a pixel defined by the gate line and the data line, includes a data driver inputting an image signal to the pixel through the data line, a panel test unit determining the occurrence or not of an error of the gate line or the data line, and a switching unit selectively connecting the data driver or the panel test unit to the display panel.

Abstract: The present invention relates to a method and device for distributing idle UE by a carrier in eNB of a multi-carrier based mobile communication system. The method of distributing idle UE in a multi-carrier based mobile communication system according to the present invention includes a process of determining a search rate by a carrier on the basis of information representing load on the carrier, a step of determining a cell reselection priority on the idle UE on the basis of the determined search rate, and a process of transmitting the determined cell reselection priority to the idle UE.

Abstract: A memory system includes at least one memory device. The at least one memory device includes a plurality of memory areas. The memory system includes a device allocation manager and security erase circuitry. The device allocation manager determines which of the plurality of memory areas is allocated or released based on a request input from at least one host. The security erase circuitry stores a security erase task for a first memory area, which is associated with a release determined by the device allocation manager, in an erase job queue, and removes the security erase task from the erase job queue when the first memory area is reallocated to a first host to which the first memory area was allocated before the release.