Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Abstract: Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Abstract: Disclosed are novel electrolytes, and techniques for making and devices using such electrolytes, which are based on compressed gas solvents. Unlike conventional electrolytes, disclosed electrolytes are based on “compressed gas solvents” mixed with various salts, referred to as “compressed gas electrolytes.” Various embodiments of a compressed gas solvent includes a material that is in a gas phase and has a vapor pressure above an atmospheric pressure at a room temperature. The disclosed compressed gas electrolytes can have wide electrochemical potential windows, high conductivity, low temperature capability and/or high pressure solvent properties. Examples of a class of compressed gases that can be used as solvent for electrolytes include hydrofluorocarbons, in particular fluoromethane, difluoromethane, tetrafluoroethane, pentafluoroethane. Also disclosed are battery and supercapacitor structures that use compressed gas solvent-based electrolytes, techniques for constructing such energy storage devices.

Abstract: Disclosed are novel electrolytes, and techniques for making and devices using such electrolytes, which are based on compressed gas solvents. Unlike conventional electrolytes, disclosed electrolytes are based on “compressed gas solvents” mixed with various salts, referred to as “compressed gas electrolytes.” Various embodiments of a compressed gas solvent includes a material that is in a gas phase and has a vapor pressure above an atmospheric pressure at a room temperature. The disclosed compressed gas electrolytes can have wide electrochemical potential windows, high conductivity, low temperature capability and/or high pressure solvent properties. Examples of a class of compressed gases that can be used as solvent for electrolytes include hydrofluorocarbons, in particular fluoromethane, difluoromethane, tetrafluoroethane, pentafluoroethane. Also disclosed are battery and supercapacitor structures that use compressed gas solvent-based electrolytes, techniques for constructing such energy storage devices.

Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

Abstract: A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Abstract: A device, an operating method of a memory controller, a memory device, and a compute express link (CXL) memory expansion device all for managing a row hammer are provided. The device includes a volatile memory and a memory controller that is configured to detect, based on input row addresses, a pattern size of a row hammer attack pattern and a row distribution of row hammer addresses, to determine, according to a type of the row distribution, whether to perform refresh management, and for every L access corresponding to the pattern size, to provide, to the volatile memory, a refresh management command and a target row address, where L is an integer greater than or equal to 1.

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Abstract: A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

Abstract: Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.