Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Abstract: A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

Abstract: A method of stably preparing an aluminum composite with excellent mechanical properties while the temperature of molten aluminum is maintained at 950° C. or less, includes mixing aluminum powder, a source material for titanium, a source material for a nonmetallic element that is able to be combined with titanium to form a compound, and an active material to prepare a precursor; adding the precursor to molten aluminum; and casting the molten aluminum.

Abstract: A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.

Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

Abstract: A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

Abstract: A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

Abstract: A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.

Abstract: Provided are a high-molecular weight polyimide used for a gas separation membrane and a method for synthesizing the same. The polyimide contains 4,4?-(hexafluoroisopropylidene)diphthalic anhydride, 2,3,5,6-tetramethyl-1,4-phenylenediamine, and 1,3-bis[2-(4-aminophenyl)-2-propyl]-benzene. According to the present invention, a gas separation membrane having high oxygen permeability and high oxygen selectivity may be provided.

Abstract: The present invention provides a method for preparing an aluminum matrix composite by infiltrating aluminum into a preform within a short period of time without a pressurization configuration using a special device as compared to the existing pressure infiltration method. According to one aspect of the present invention, provided is a method for preparing an aluminum matrix composite using pressureless infiltration, the method including: preparing a preform formed of a mixture of raw powders capable of forming ceramic through a combustion synthesis reaction; immersing the preform in an aluminum melt, in which a part of the preform is exposed to an external environment without being immersed in the aluminum melt; and infiltrating molten aluminum into the preform while causing a combustion synthesis reaction in the preform.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.