Patents by Inventor Jung-Myung CHOI
Jung-Myung CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105099Abstract: The embodiment relates to a data driving device for driving pixels of a display panel. In the data driving device, two adjacent DACs can have different gate loads for the same gray level value so that the fluctuation of the gate load according to the gray level value is reduced.Type: ApplicationFiled: November 17, 2023Publication date: March 28, 2024Applicant: LX SEMICON CO., LTD.Inventors: Da Sol WON, Kwang Myung KANG, Yong Min KIM, Dong Keun SONG, Jung Min CHOI, Seon Ho HONG
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Patent number: 11012077Abstract: An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.Type: GrantFiled: July 31, 2019Date of Patent: May 18, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-kyun Shin, Myoung-bo Kwak, Jong-shin Shin, Jung-myung Choi, Jin-wook Burm, Chang-zhi Yu, Dae-wung Lee
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Patent number: 10992447Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: September 17, 2020Date of Patent: April 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Publication number: 20210006387Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: HAN SOO LEE, SUNG JUN KIM, CHAE RYUNG KIM, DONG UK PARK, YOUN WOONG CHUNG, JUNG MYUNG CHOI, HAN KYUL LIM, GYEONG HAN CHA
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Patent number: 10790958Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: April 25, 2019Date of Patent: September 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Publication number: 20200119739Abstract: An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.Type: ApplicationFiled: July 31, 2019Publication date: April 16, 2020Applicants: Samsung Electronics Co., Ltd., SOGANG UNIVERSITY RESEARCH FOUNDATIONInventors: Seong-kyun SHIN, Myoung-bo KWAK, Jong-shin SHIN, Jung-myung CHOI, Jin-wook BURM, Chang-zhi YU, Dae-wung LEE
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Publication number: 20190260569Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: April 25, 2019Publication date: August 22, 2019Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Patent number: 10313101Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: August 27, 2018Date of Patent: June 4, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Publication number: 20190058574Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: August 27, 2018Publication date: February 21, 2019Inventors: HAN SOO LEE, SUNGJUN KIM, CHAE RYUNG KIM, DONG UK PARK, YOUN WOONG CHUNG, JUNG MYUNG CHOI, HAN KYUL LIM, GYEONG HAN CHA
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Patent number: 10075283Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: August 3, 2017Date of Patent: September 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Patent number: 9832005Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: January 27, 2016Date of Patent: November 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Publication number: 20170331616Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Inventors: HAN SOO LEE, SUNG JUN KIM, CHAE RYUNG KIM, DONG UK PARK, YOUN WOONG CHUNG, JUNG MYUNG CHOI, HAN KYUL LIM, GYEONG HAN CHA
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Publication number: 20160142199Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: January 27, 2016Publication date: May 19, 2016Inventors: HAN SOO LEE, SUNG JUN KIM, CHAE RYUNG KIM, DONG UK PARK, YOUN WOONG CHUNG, JUNG MYUNG CHOI, HAN KYUL LIM, GYEONG HAN CHA
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Patent number: 9281935Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: GrantFiled: October 14, 2014Date of Patent: March 8, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
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Publication number: 20150229467Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.Type: ApplicationFiled: October 14, 2014Publication date: August 13, 2015Inventors: HAN SOO LEE, SUNG JUN KIM, CHAE RYUNG KIM, DONG UK PARK, Youn Woong CHUNG, JUNG MYUNG CHOI, HAN KYUL LIM, GYEONG HAN CHA
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Patent number: 9071237Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.Type: GrantFiled: March 13, 2014Date of Patent: June 30, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon-Oh Lee, Tae-Pyeong Kim, Jung-Myung Choi, Sung-Jun Kim, Ho-Bin Song, Han-Kyul Lim
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Publication number: 20140266362Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon-Oh LEE, Tae-Pyeong KIM, Jung-Myung CHOI, Sung-Jun KIM, Ho-Bin SONG, Han-Kyul LIM