Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Abstract: A memory device comprises: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a first memory cell in the memory cell region, and a second memory cell different from the first memory cell in the memory cell region, wherein the first memory cell and the second memory cell are included in a same memory block as each other, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region, different from the first word line, connected to the second memory cell, an address decoder in the peripheral circuit region configured to apply one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines, and a control logic in the peripheral circuit region configured to control an erasing operation on the memory block, using the address decoder, wherein

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The method includes performing a plurality of program operations on a plurality of memory cells each to be programmed to one of a plurality of program states, performing a program-verify operation on programmed memory cells associated with each of the plurality of program states, the program-verify operation comprises, selecting one of the plurality of offsets based on a noise level of a common source line associated with a programmed memory cell, using the selected offset to select one of a first verify voltage and a second verify voltage higher than the first verify voltage, and verifying a program state of the programmed memory cell using the first verify voltage and the second verify voltage.

Abstract: A nonvolatile memory device programs a memory cell by performing a plurality of program loops each comprising a program operation and a program verifying operation. Where the program verifying operation in one program loop determines that the memory cell has been successfully programmed to a target state, a soft-programming operation is performed in a subsequent program loop to determine whether the memory cell has retained the target state, and if not, increases the threshold voltage of the memory cell.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The method includes performing a plurality of program operations on a plurality of memory cells each to be programmed to one of a plurality of program states, performing a program-verify operation on programmed memory cells associated with each of the plurality of program states, the program-verify operation comprises, selecting one of the plurality of offsets based on a noise level of a common source line associated with a programmed memory cell, using the selected offset to select one of a first verify voltage and a second verify voltage higher than the first verify voltage, and verifying a program state of the programmed memory cell using the first verify voltage and the second verify voltage.

Abstract: A nonvolatile memory device programs a memory cell by performing a plurality of program loops each comprising a program operation and a program verifying operation. Where the program verifying operation in one program loop determines that the memory cell has been successfully programmed to a target state, a soft-programming operation is performed in a subsequent program loop to determine whether the memory cell has retained the target state, and if not, increases the threshold voltage of the memory cell.