Patents by Inventor Jung-Piao Chiu

Jung-Piao Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357914
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10700205
    Abstract: A method for forming a semiconductor structure includes receiving a substrate including a dielectric structure; forming a first recess in the substrate; forming a dielectric spacer over a sidewall of the first recess; forming a first semiconductor layer to fill the first recess; removing the dielectric structure to form a second recess over the substrate; and forming a second semiconductor layer to fill the second recess. The dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Publication number: 20190259877
    Abstract: A method for forming a semiconductor structure includes receiving a substrate including a dielectric structure; forming a first recess in the substrate; forming a dielectric spacer over a sidewall of the first recess; forming a first semiconductor layer to fill the first recess; removing the dielectric structure to form a second recess over the substrate; and forming a second semiconductor layer to fill the second recess. The dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: CHAO-CHING CHENG, CHEN-FENG HSU, YU-LIN YANG, JUNG-PIAO CHIU, TZU-CHIANG CHEN
  • Patent number: 10283639
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Publication number: 20190097053
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: CHAO-CHING CHENG, CHEN-FENG HSU, YU-LIN YANG, JUNG-PIAO CHIU, TZU-CHIANG CHEN
  • Publication number: 20180350971
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10062782
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10038080
    Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with the first dummy gate; forming a spacer layer in contact with the first dummy gate and the epitaxy structure; and replacing the first dummy gate with a metal gate stack.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Jung-Piao Chiu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Publication number: 20180151717
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: February 10, 2017
    Publication date: May 31, 2018
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 9659826
    Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20170084498
    Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Chang, Yee-Chia Yeo
  • Patent number: 9515071
    Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20160190136
    Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20160172247
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Chia-Cheng Ho, Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee, Jung-Piao Chiu
  • Patent number: 9349652
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee, Jung-Piao Chiu