Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

Abstract: A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: A semiconductor device includes a memory cell having a bottom electrode, a memory element, a selector, a top electrode and a connecting structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connecting structure is electrically connecting the memory element to the selector, wherein the connecting structure includes a base portion and a pillar portion. The base portion disposed on the memory element. The pillar portion is disposed on the base portion, wherein the pillar portion is physically connected to the selector, and includes a tapered pillar foot.

Abstract: A memory cell includes a bottom electrode, a memory element, a selector, a top electrode and a connecting structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connecting structure is electrically connecting the memory element to the selector, wherein the connecting structure includes a base portion and a pillar portion. The base portion disposed on the memory element. The pillar portion is disposed on the base portion, wherein the pillar portion is physically connected to the selector, and includes a tapered pillar foot.

Abstract: A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.

Abstract: A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: Manufacture of a ferroelectric random-access memory device includes forming a first electrode and an intermetal dielectric (IMD) layer over the first electrode. The IMD layer has a first surface on a first side of the IMD layer distal from the first electrode and a second surface on a second side of the IMD layer proximate to the first electrode. A via is created through the IMD layer, which is aligned with the first electrode underneath and has a side wall extending from the first surface of the IMD layer to the second surface of the IMD layer. A ferroelectric layer is deposited over the IMD layer. The ferroelectric layer includes a first part within the via and a second part extending laterally out from the via over the first surface of the IMD layer, the second part thereafter being removed by chemical mechanical polishing.

Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.