Abstract: In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.

Abstract: The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.

Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.

Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.

Abstract: A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

Abstract: A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

Abstract: A delay locked loop includes a first delay line and a second delay line. The first delay line is configured to generate a first delay clock, signal by passing an input clock, signal through a first number of logic gates among a plurality of logic gates and a second delay clock signal by passing the input clock signal through a second number of logic gates among the plurality of logic gates. The second delay line is configured to output an output clock signal based on one of a first signal having a first phase of the first delay clock signal, a second signal having a second phase of the second delay clock signal, and an interpolation signal having a third phase adjusted in stages by a reference value between the first phase and the second phase.

Abstract: A clock data recovery device includes a clock recovery device for separating a recovery clock signal and a data signal from an input signal and generating a clock fail signal in response to noise of the input signal; a clock generator for receiving a control voltage to generate one or more delay clock signals, delaying the recovery clock signal to generate the delay clock signals in a first mode, delaying the generated delay clock signal to generate the delay clock signal in a second mode, and switching the first mode to the second mode in response to the clock fail signal; and a phase frequency detector for comparing at least one of the delay clock signals with the recovery clock signal to generate a voltage adjusting signal; and a control voltage generator for receiving the voltage adjusting signal to generate the control voltage.

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: A source driver integrated circuit (IC) includes a logic circuit configured to receive a transmission data packet including data, a compression code indicating compression or non-compression of the data, and a clock signal, to interpret the compression code, and to generate a sleep mode enable signal based on an interpretation result, and a clock signal recovery circuit configured to enable one of a voltage-controlled delay line and a voltage-controller oscillator in response to the sleep mode enable signal.

Abstract: A system for transmitting and receiving a signal includes a transmitter that switches a first reference voltage and a second reference voltage and generates first and second voltage signals, and a receiver the receives the first and second voltage signals. The transmitter includes a reference voltage generator that generates the first reference voltage and the second reference voltage, and a switch block that switches the first reference voltage and the second reference voltage and outputs the first and second voltage signals. The receiver includes a resistor having two terminals to which the first and second voltage signals are applied.

Abstract: A delay-locked loop circuit includes a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed from one another to produce an earliest delayed clock signal to a latest delayed clock signal, the voltage-controlled delay line including an anti-jitter delay circuit and a plurality of delay circuits, the anti-jitter delay circuit configured to output the earliest delayed clock signal, and the plurality of delay circuits coupled in series and configured to output a remainder of the plurality of delayed clock signals, a phase frequency detection circuit configured to generate an up signal and a down signal based on the earliest delayed clock signal and the latest delayed clock signal, a filter configured to generate the voltage control signal in response to the up signal and the down signal, and a lock detection circuit configured to generate

Abstract: A delay-locked loop circuit includes a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed from one another to produce an earliest delayed clock signal to a latest delayed clock signal, the voltage-controlled delay line including an anti-jitter delay circuit and a plurality of delay circuits, the anti-jitter delay circuit configured to output the earliest delayed clock signal, and the plurality of delay circuits coupled in series and configured to output a remainder of the plurality of delayed clock signals, a phase frequency detection circuit configured to generate an up signal and a down signal based on the earliest delayed clock signal and the latest delayed clock signal, a filter configured to generate the voltage control signal in response to the up signal and the down signal, and a lock detection circuit configured to generate

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: A system for transmitting and receiving a signal includes a transmitter that switches a first reference voltage and a second reference voltage and generates first and second voltage signals, and a receiver the receives the first and second voltage signals. The transmitter includes a reference voltage generator that generates the first reference voltage and the second reference voltage, and a switch block that switches the first reference voltage and the second reference voltage and outputs the first and second voltage signals. The receiver includes a resistor having two terminals to which the first and second voltage signals are applied.

Abstract: An interface method for a data transmitting and receiving system including a transmitter and a receiver includes; resetting the receiver in response to a data stream communicated from the transmitter or upon detecting power-up of the transmitter or receiver, and operating the receiver in response to a current data stream received from the transmitter, wherein the operating of the receiver comprises at least one of; (a) updating data stored in the receiver according to control data contained in the current data stream, and (b) receiving payload data contained in the current data stream.

Abstract: A data driving unit and a liquid crystal display (LCD) are provided. The data driving unit includes a first buffer, a second buffer, a charge sharing switch connected between an output terminal of the first buffer and an output terminal of the second buffer, and a controller configured to compare a previous line-time data pattern with a current line-time data pattern and generate a control signal for controlling a switching operation of the charge sharing switch according to a comparison result.