Patents by Inventor Jung Rung Jiang
Jung Rung Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694732Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: GrantFiled: May 2, 2022Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
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Publication number: 20220254392Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: ApplicationFiled: May 2, 2022Publication date: August 11, 2022Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
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Patent number: 11322185Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: GrantFiled: December 10, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
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Publication number: 20210090618Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: ApplicationFiled: December 10, 2020Publication date: March 25, 2021Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
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Patent number: 10867642Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: GrantFiled: November 2, 2016Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
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Patent number: 9847318Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.Type: GrantFiled: February 15, 2016Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
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Publication number: 20170337955Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.Type: ApplicationFiled: November 2, 2016Publication date: November 23, 2017Inventors: HSIN-CHENG CHEN, JUNG-RUNG JIANG, YEN-HAO HUANG
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Publication number: 20160163680Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
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Patent number: 9269640Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.Type: GrantFiled: October 31, 2013Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
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Publication number: 20150115329Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
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Patent number: 6766360Abstract: A computer network system for manipulating requests for shared data includes a plurality of groups and each group has a plurality of nodes and each node has a plurality of processors. The system further comprises a request outstanding buffer (ROB) for recording data requests, a remote access cache (RAC) for caching the results of prior memory requests which are remote to a requesting node, and a directory for recording a global state of a cache line in the system. The RAC supports only two states, Shared and Invalid, and caches only clean remote data. If the directory state is Modified/Exclusive, the line is indicated to not be in the RAC. The behavior of the RAC is described for two important cases: initial RAC does not have the line caches and initial RAC has the line cached.Type: GrantFiled: July 14, 2000Date of Patent: July 20, 2004Assignee: Fujitsu LimitedInventors: Patrick N. Conway, Yukihiro Nakagawa, Jung Rung Jiang