Patents by Inventor Jung Rung Jiang

Jung Rung Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210090618
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Application
    Filed: December 10, 2020
    Publication date: March 25, 2021
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Patent number: 10867642
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Patent number: 9847318
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
  • Publication number: 20170337955
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 23, 2017
    Inventors: HSIN-CHENG CHEN, JUNG-RUNG JIANG, YEN-HAO HUANG
  • Publication number: 20160163680
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
  • Patent number: 9269640
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
  • Publication number: 20150115329
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
  • Patent number: 6766360
    Abstract: A computer network system for manipulating requests for shared data includes a plurality of groups and each group has a plurality of nodes and each node has a plurality of processors. The system further comprises a request outstanding buffer (ROB) for recording data requests, a remote access cache (RAC) for caching the results of prior memory requests which are remote to a requesting node, and a directory for recording a global state of a cache line in the system. The RAC supports only two states, Shared and Invalid, and caches only clean remote data. If the directory state is Modified/Exclusive, the line is indicated to not be in the RAC. The behavior of the RAC is described for two important cases: initial RAC does not have the line caches and initial RAC has the line cached.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: July 20, 2004
    Assignee: Fujitsu Limited
    Inventors: Patrick N. Conway, Yukihiro Nakagawa, Jung Rung Jiang