Abstract: A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.

Abstract: A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.

Abstract: A three-dimensional (3D) semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a conductive pattern and a second insulation pattern. The conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be configured to physically contact an upper surface of the conductive pattern. The second insulation pattern may have a property different from a property of the first insulation pattern. The vertical channel structure may be formed through the stack structure.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.

Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.

Abstract: A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.