Patents by Inventor Jung Ryul Ahn

Jung Ryul Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230301102
    Abstract: A three-dimensional (3D) semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a conductive pattern and a second insulation pattern. The conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be configured to physically contact an upper surface of the conductive pattern. The second insulation pattern may have a property different from a property of the first insulation pattern. The vertical channel structure may be formed through the stack structure.
    Type: Application
    Filed: December 20, 2022
    Publication date: September 21, 2023
    Applicant: SK hynix Inc.
    Inventor: Jung Ryul AHN
  • Publication number: 20230301103
    Abstract: A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.
    Type: Application
    Filed: December 20, 2022
    Publication date: September 21, 2023
    Applicant: SK hynix Inc.
    Inventors: Seung Min LEE, Jung Ryul AHN
  • Patent number: 11665904
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 30, 2023
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 11610915
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Sang Yong Lee, Sang Min Kim, Jung Ryul Ahn, Sang Hyun Oh, Seung Bum Cha, Kang Sik Choi
  • Publication number: 20210249441
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Application
    Filed: April 28, 2021
    Publication date: August 12, 2021
    Applicant: SK hynix Inc.
    Inventors: Sang Yong LEE, Sang Min KIM, Jung Ryul AHN, Sang Hyun OH, Seung Bum CHA, Kang Sik CHOI
  • Patent number: 11024647
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 1, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Yong Lee, Sang Min Kim, Jung Ryul Ahn, Sang Hyun Oh, Seung Bum Cha, Kang Sik Choi
  • Publication number: 20210134836
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Jung Ryul AHN
  • Patent number: 10930667
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Publication number: 20200312879
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: SK hynix Inc.
    Inventors: Sang Yong LEE, Sang Min KIM, Jung Ryul AHN, Sang Hyun OH, Seung Bum CHA, Kang Sik CHOI
  • Patent number: 10727247
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Yong Lee, Sang Min Kim, Jung Ryul Ahn, Sang Hyun Oh, Seung Bum Cha, Kang Sik Choi
  • Publication number: 20190280006
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Application
    Filed: November 5, 2018
    Publication date: September 12, 2019
    Applicant: SK hynix Inc.
    Inventors: Sang Yong LEE, Sang Min KIM, Jung Ryul AHN, Sang Hyun OH, Seung Bum CHA, Kang Sik CHOI
  • Patent number: 10163924
    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc. Gyeonggi-do
    Inventor: Jung Ryul Ahn
  • Patent number: 10115809
    Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yun Kyoung Lee, Jung Ryul Ahn
  • Publication number: 20180204850
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Applicant: SK hynix Inc.
    Inventor: Jung Ryul AHN
  • Patent number: 9960177
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 1, 2018
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 9767906
    Abstract: A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 19, 2017
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Publication number: 20170162594
    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.
    Type: Application
    Filed: May 5, 2016
    Publication date: June 8, 2017
    Inventor: Jung Ryul AHN
  • Patent number: 9633731
    Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 25, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jung Ryul Ahn, Yun Kyoung Lee
  • Publication number: 20170092363
    Abstract: A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.
    Type: Application
    Filed: February 10, 2016
    Publication date: March 30, 2017
    Inventor: Jung Ryul AHN
  • Patent number: 9601207
    Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 21, 2017
    Assignee: SK HYNIX INC.
    Inventors: Yong Dae Park, Eun Seok Choi, Jung Ryul Ahn, Se Hoon Kim, In Geun Lim, Jung Seok Oh