Patents by Inventor Jung S. Hoei
Jung S. Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126448Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Inventors: Animesh R. Chowdhury, Kishore K. Muchherla, Nicola Ciocchini, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
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Patent number: 11922029Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.Type: GrantFiled: July 12, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Ugo Russo
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Publication number: 20240071522Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Nicola Ciocchini, Animesh R. Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
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Patent number: 9158612Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.Type: GrantFiled: October 4, 2013Date of Patent: October 13, 2015Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8719665Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: GrantFiled: October 17, 2013Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20140053033Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: ApplicationFiled: October 17, 2013Publication date: February 20, 2014Applicant: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20140040683Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: Mocron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8611149Abstract: A solid state drive is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, including an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.Type: GrantFiled: March 18, 2011Date of Patent: December 17, 2013Assignee: Micron TechnologyInventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8578244Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: GrantFiled: October 2, 2012Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8400826Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.Type: GrantFiled: August 21, 2012Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20120314503Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8291271Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: GrantFiled: January 9, 2012Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8259491Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.Type: GrantFiled: April 26, 2011Date of Patent: September 4, 2012Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20120106249Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8102706Abstract: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.Type: GrantFiled: April 29, 2010Date of Patent: January 24, 2012Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8103940Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: GrantFiled: August 2, 2011Date of Patent: January 24, 2012Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20110289387Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Patent number: 8006166Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.Type: GrantFiled: June 12, 2007Date of Patent: August 23, 2011Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20110199831Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
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Publication number: 20110164449Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.Type: ApplicationFiled: March 18, 2011Publication date: July 7, 2011Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei