Patents by Inventor Jung Seock Lee

Jung Seock Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7986049
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ki-Won Nam
  • Publication number: 20100276789
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Application
    Filed: July 15, 2010
    Publication date: November 4, 2010
    Inventors: Jung-Seock LEE, Ki-Won NAM
  • Patent number: 7781347
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ki-Won Nam
  • Patent number: 7732335
    Abstract: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist pattern until a remaining carbon-based material portion has a predetermined thickness, etching the remaining carbon-based material portion until a corresponding metal layer portion is exposed to form a carbon-based material pattern, and etching the metal layer by using the carbon-based material pattern to form a hard mask pattern for forming the pattern.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 8, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7709369
    Abstract: A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes using a fluorocarbon gas and the second post treatment includes using a nitrogen trifluoride (NF3) gas.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7678535
    Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7629242
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom surface of the recess pattern while protecting sidewalls of the recess pattern, performing an isotropic etching process onto a bottom portion of the recess pattern, and forming a gate pattern partially buried into the recess pattern after the isotropic etching process is performed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Jung-Seock Lee
  • Patent number: 7608536
    Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung Seock Lee, Hyun Suk Sung
  • Publication number: 20090004847
    Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.
    Type: Application
    Filed: November 13, 2007
    Publication date: January 1, 2009
    Inventors: Jung Seock Lee, Hyun Suk Sung
  • Publication number: 20080242042
    Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer and a support layer on a substrate. A plurality of openings are formed by etching the support layer and the sacrificial layer. An electrode is formed in inner walls of the openings including sidewalls of the support layer patterned through etching. A portion of the patterned support layer is removed, and the sacrificial layer is also removed.
    Type: Application
    Filed: June 29, 2007
    Publication date: October 2, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jong-Kuk KIM, Jung-Seock Lee, Phil-Goo Kong, Hyun Ahn
  • Publication number: 20080157403
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Application
    Filed: June 28, 2007
    Publication date: July 3, 2008
    Inventors: Jung-Seock Lee, Ki-Won Nam
  • Publication number: 20080160765
    Abstract: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist pattern until a remaining carbon-based material portion has a predetermined thickness, etching the remaining carbon-based material portion until a corresponding metal layer portion is exposed to form a carbon-based material pattern, and etching the metal layer by using the carbon-based material pattern to form a hard mask pattern for forming the pattern.
    Type: Application
    Filed: June 29, 2007
    Publication date: July 3, 2008
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Publication number: 20080108216
    Abstract: A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes using a fluorocarbon gas and the second post treatment includes using a nitrogen trifluoride (NF3) gas.
    Type: Application
    Filed: February 26, 2007
    Publication date: May 8, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jung-Seock LEE, Ky-Hyun Han
  • Publication number: 20080081448
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer, a first electrode layer, a second electrode layer, and a hard mask over a substrate, etching the second electrode layer to form second electrodes with recessed sidewalls, forming a passivation layer over a resultant surface profile provided after forming the second electrodes, performing an etch-back process on the passivation layer, and etching the first electrode layer exposed by the etch-back process to form first electrodes.
    Type: Application
    Filed: June 28, 2007
    Publication date: April 3, 2008
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Publication number: 20070105388
    Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 10, 2007
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Publication number: 20070099384
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom surface of the recess pattern while protecting sidewalls of the recess pattern, performing an isotropic etching process onto a bottom portion of the recess pattern, and forming a gate pattern partially buried into the recess pattern after the isotropic etching process is performed.
    Type: Application
    Filed: June 29, 2006
    Publication date: May 3, 2007
    Inventors: Ky-Hyun Han, Jung-Seock Lee