Patents by Inventor Jung-seok Ahn
Jung-seok Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014087Abstract: A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.Type: ApplicationFiled: February 23, 2023Publication date: January 11, 2024Inventors: In Sup SHIN, Jung-Seok Ahn, Hyeong Mun Kang, Seung Woo Sim
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Patent number: 10748875Abstract: A method of manufacturing a semiconductor memory apparatus, in which a plurality of memory dies are stacked, includes forming first memory dies on a wafer. An under-fill material is deposited on a wafer, on which the first memory dies are formed, to form a first part of an under-fill layer. A first portion of the under-fill layer remaining on top surfaces of the first memory dies is removed by performing a half sawing process, and parts of edge portions of the first memory dies are removed during the removal of the first portion of the under-fill layer to form first cavities. Second memory dies are formed on the first memory dies. The under-fill material is deposited on the wafer including the second memory dies formed thereon to form a second part of the under-fill layer on a remaining part of the under-fill layer.Type: GrantFiled: February 26, 2019Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Jung Seok Ahn
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Publication number: 20200118976Abstract: A method of manufacturing a semiconductor memory apparatus, in which a plurality of memory dies are stacked, includes forming first memory dies on a wafer. An under-fill material is deposited on a wafer, on which the first memory dies are formed, to form a first part of an under-fill layer. A first portion of the under-fill layer remaining on top surfaces of the first memory dies is removed by performing a half sawing process, and parts of edge portions of the first memory dies are removed during the removal of the first portion of the under-fill layer to form first cavities. Second memory dies are formed on the first memory dies. The under-fill material is deposited on the wafer including the second memory dies formed thereon to form a second part of the under-fill layer on a remaining part of the under-fill layer.Type: ApplicationFiled: February 26, 2019Publication date: April 16, 2020Applicant: Samsung Electronics Co., Ltd.Inventor: Jung Seok AHN
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Patent number: 10157766Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.Type: GrantFiled: March 19, 2014Date of Patent: December 18, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Joonsik Sohn, Jung-Seok Ahn, Chungsun Lee, Taeje Cho
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Publication number: 20170004990Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.Type: ApplicationFiled: March 19, 2014Publication date: January 5, 2017Inventors: Un-Byoung Kang, Joonsik Sohn, Jung-Seok Ahn, Chungsun Lee, Taeje Cho
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Patent number: 9412707Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.Type: GrantFiled: May 1, 2015Date of Patent: August 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-soo Chung, Tae-je Cho, Jung-seok Ahn, In-young Lee
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Patent number: 9412636Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.Type: GrantFiled: April 9, 2015Date of Patent: August 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chungsun Lee, Jung-Seok Ahn, Kwang-chul Choi, Un-Byoung Kang, Jung-Hwan Kim, Joonsik Sohn, Jeon Il Lee
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Publication number: 20150364432Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.Type: ApplicationFiled: May 1, 2015Publication date: December 17, 2015Inventors: Hyun-soo CHUNG, Tae-je CHO, Jung-seok AHN, In-young LEE
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Publication number: 20150318268Abstract: A multi-chip package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first active surface. The second semiconductor chip has a second active surface facing the first active surface. The second active surface is electrically connected with the first active surface and the first active surface of the first semiconductor chip and the second active surface of the second semiconductor chip are bonded to each other without an adhesive.Type: ApplicationFiled: April 27, 2015Publication date: November 5, 2015Inventors: JUNG-SEOK AHN, SANG-WON KIM, YOUNG-SANG CHO, KWANG-CHUL CHOI, SUNG-EUN PYO
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Patent number: 9136260Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: GrantFiled: December 2, 2013Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Publication number: 20150221517Abstract: A method of manufacturing a semiconductor device capable of thinning a semiconductor chip can be performed while preventing the semiconductor chip from being damaged. A method of manufacturing a semiconductor device includes: preparing a semiconductor substrate including a plurality of semiconductor chips, attaching the semiconductor substrate to a support substrate with an adhesive support film, removing an edge region of the semiconductor substrate together with a portion of the adhesive support film between the edge region of the semiconductor substrate and the support substrate and, thereafter, polishing the semiconductor substrate to thin the semiconductor substrate.Type: ApplicationFiled: February 4, 2015Publication date: August 6, 2015Inventors: Eun-mi Kim, Un-byoung Kang, Tae-je Cho, Jung-seok Ahn
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Publication number: 20150214089Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.Type: ApplicationFiled: April 9, 2015Publication date: July 30, 2015Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: CHUNGSUN LEE, Jung-Seok AHN, Kwang-chul CHOI, Un-Byoung KANG, Jung-Hwan KIM, JOONSIK SOHN, JEON IL LEE
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Patent number: 9023716Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.Type: GrantFiled: January 6, 2014Date of Patent: May 5, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Chungsun Lee, Jung-Seok Ahn, Kwang-chul Choi, Un-Byoung Kang, Jung-Hwan Kim, Joonsik Sohn, Jeon Il Lee
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Patent number: 9006081Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.Type: GrantFiled: June 22, 2012Date of Patent: April 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Seok Ahn, Il Hwan Kim, Jung-Hwan Kim, Sangwook Park, Chungsun Lee, Kwang-chul Choi
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Publication number: 20140210075Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.Type: ApplicationFiled: January 6, 2014Publication date: July 31, 2014Applicant: Samsung Electronics Co., LtdInventors: CHUNGSUN LEE, Jung-Seok AHN, Kwang-chul CHOI, Un-Byoung KANG, Jung-Hwan KIM, JOONSIK SOHN, JEON IL LEE
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Publication number: 20140154839Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: ApplicationFiled: December 2, 2013Publication date: June 5, 2014Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Patent number: 8637350Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: GrantFiled: April 4, 2012Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Publication number: 20120329249Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.Type: ApplicationFiled: June 22, 2012Publication date: December 27, 2012Inventors: Jung-Seok Ahn, II Hwan Kim, Jung-Hwan Kim, Sangwook Park, Chungsun Lee, Kwang-chul Choi
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Publication number: 20120282735Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: ApplicationFiled: April 4, 2012Publication date: November 8, 2012Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park