Patents by Inventor Jung Seok Oh
Jung Seok Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9831264Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.Type: GrantFiled: March 1, 2016Date of Patent: November 28, 2017Assignee: SK Hynix Inc.Inventors: Eun-Seok Choi, Sa-Yong Shim, In-Hey Lee, Sung-Wook Jung, Jung-Seok Oh
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Patent number: 9691490Abstract: The semiconductor memory device includes a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate, a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells, and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are is replaced with a dummy memory cell from among the second plurality of dummy memory cells.Type: GrantFiled: August 4, 2014Date of Patent: June 27, 2017Assignee: SK hynix Inc.Inventors: Eun Seok Choi, Jung Seok Oh
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Patent number: 9601207Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.Type: GrantFiled: September 28, 2015Date of Patent: March 21, 2017Assignee: SK HYNIX INC.Inventors: Yong Dae Park, Eun Seok Choi, Jung Ryul Ahn, Se Hoon Kim, In Geun Lim, Jung Seok Oh
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Patent number: 9520198Abstract: An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.Type: GrantFiled: December 15, 2014Date of Patent: December 13, 2016Assignee: SK Hynix Inc.Inventors: Se Kyoung Choi, Eun Seok Choi, Jung Seok Oh
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Publication number: 20160181275Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.Type: ApplicationFiled: March 1, 2016Publication date: June 23, 2016Inventors: Eun-Seok CHOI, Sa-Yong SHIM, In-Hey LEE, Sung-Wook JUNG, Jung-Seok OH
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Patent number: 9306040Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.Type: GrantFiled: July 17, 2013Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Eun-Seok Choi, Sa-Yong Shim, In-Hey Lee, Sung-Wook Jung, Jung-Seok Oh
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Publication number: 20160027520Abstract: An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.Type: ApplicationFiled: December 15, 2014Publication date: January 28, 2016Inventors: Se Kyoung CHOI, Eun Seok CHOI, Jung Seok OH
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Publication number: 20160019966Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Inventors: Yong Dae PARK, Eun Seok CHOI, Jung Ryul AHN, Se Hoon KIM, In Geun LIM, Jung Seok OH
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Patent number: 9176873Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.Type: GrantFiled: December 19, 2012Date of Patent: November 3, 2015Assignee: SK Hynix Inc.Inventors: Yong Dae Park, Eun Seok Choi, Jung Ryul Ahn, Se Hoon Kim, In Geun Lim, Jung Seok Oh
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Publication number: 20150228352Abstract: The semiconductor memory device includes a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate, a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells, and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are is replaced with a dummy memory cell from among the second plurality of dummy memory cells.Type: ApplicationFiled: August 4, 2014Publication date: August 13, 2015Inventors: Eun Seok CHOI, Jung Seok OH
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Publication number: 20140299931Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.Type: ApplicationFiled: July 17, 2013Publication date: October 9, 2014Inventors: Eun-Seok CHOI, Sa-Yong SHIM, In-Hey LEE, Sung-Wook JUNG, Jung-Seok OH
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Patent number: 8854855Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.Type: GrantFiled: March 14, 2013Date of Patent: October 7, 2014Assignee: SK Hynix Inc.Inventors: Sung Wook Jung, Jung Seok Oh
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Patent number: 8743612Abstract: A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N?1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.Type: GrantFiled: September 6, 2012Date of Patent: June 3, 2014Assignee: SK Hynix Inc.Inventors: Eun Seok Choi, Jung Ryul Ahn, Se Hoon Kim, Yong Dae Park, In Geun Lim, Jung Seok Oh
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Publication number: 20140112049Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.Type: ApplicationFiled: March 14, 2013Publication date: April 24, 2014Applicant: SK HYNIX INC.Inventors: Sung Wook JUNG, Jung Seok OH
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Publication number: 20140068222Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.Type: ApplicationFiled: December 19, 2012Publication date: March 6, 2014Applicant: SK HYNIX INC.Inventors: Yong Dae PARK, Eun Seok CHOI, Jung Ryul AHN, Se Hoon KIM, In Geun LIM, Jung Seok OH
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Publication number: 20130194869Abstract: A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N?1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.Type: ApplicationFiled: September 6, 2012Publication date: August 1, 2013Inventors: Eun Seok CHOI, Jung Ryul Ahn, Se Hoon Kim, Young Dae Park, In Geun Lim, Jung Seok Oh
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Patent number: 6712871Abstract: A sintered alloy composition for automotive engine valve seats, and a method for producing the same, are described. An iron base sintered alloy composition comprising vanadium carbide particles, Fe—Co—Ni—Mo alloy particles, and Cr—W—Co—C alloy particles in which the composition is dispersed in a structure of sorbite is particularly suitable for use as materials of valve seats for automotive engines which requires excellent wear resistance, high-performance, high-rotation-speed, and low-fuel-consumption.Type: GrantFiled: August 29, 2002Date of Patent: March 30, 2004Assignee: Hyundai Motor CompanyInventor: Jung Seok Oh
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Publication number: 20030233910Abstract: A sintered alloy having an improved wear resistance and a workability for a valve seat. The alloy contains iron as a main component, carbon, silicon, chromium, molybdenum, cobalt, maganese, lead, vanadium, advantageously boron nitride, and tungsten. The strength, wear resistance, and material properties are improved by a sub-zero treatment. Sintered alloy with wear resistance used for a valve seat comprises Fe as a main component, C of 1.2 to 1.7 wt %, Cr of 3.5 to 5.0 wt %, Mo of 2.0 to 4.0 wt %, V of 3.0 to 5.0 wt %, W of 7.0 to 10.0 wt %, Co of 2.0 to 3.5 wt %, boron nitride of 0.1 to 1.0 wt %, S of 0.2 to 0.4 wt %, Mn of 0.2 to 0.5 wt %, advantageously 0.2 to 0.6% Si, and Pb of 10.0 to 15.0 wt %. Sintered alloy for an valve seat is manufactured by a sub-zero treatment so that the amount of metallic particles separated from a base matrix decreases and a size of the separated metallic particle becomes small.Type: ApplicationFiled: December 31, 2002Publication date: December 25, 2003Inventors: Lim Ho Jeong, Kwang Ho Song, Jung Seok Oh, Jong Dae Lim
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Publication number: 20030097904Abstract: A sintered alloy composition for automotive engine valve seats, and a method for producing the same, are described. An iron base sintered alloy composition comprising vanadium carbide particles, Fe—Co—Ni—Mo alloy particles, and Cr—W—Co—C alloy particles in which the composition is dispersed in a structure of sorbite is particularly suitable for use as materials of valve seats for automotive engines which requires excellent wear resistance, high-performance, high-rotation-speed, and low-fuel-consumption.Type: ApplicationFiled: August 29, 2002Publication date: May 29, 2003Inventor: Jung Seok Oh
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Patent number: 6224822Abstract: A synchronizer ring of the transmission of an automobile comprising an inner ring made of the powder of sintered ferroalloy, and an outer ring made of the brass-sintered alloy, the inner ring and the outer ring are integrally united by the brazing. The synchronizer ring is manufactured by method comprising step for pressurizing the powder of the sintered ferroalloy with the pressure 6˜7 ton/cm2 and forming the body of the outer ring under the reducing atmosphere at the temperature of 1,140±20° C., step for forming the inner ring with the brass-sintered alloy and plating the outer ring with nickel, step for spreading the brazing powder on the surface of the inner ring; and step for brazing the inner ring and the outer ring and integrally uniting each other under the reducing atmosphere at the temperature of 900˜920° C. for 20˜40 minutes.Type: GrantFiled: February 25, 2000Date of Patent: May 1, 2001Assignee: Hyundai Motor CompanyInventor: Jung Seok Oh