Patents by Inventor Jungsig Jun

Jungsig Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11615287
    Abstract: The present disclosure relates to an artificial intelligence chip for processing computations for machine learning models that provides a compute node and a method of processing a computational model using a plurality of compute nodes in parallel. In some embodiments, the compute node, comprises: a communication interface configured to communicate with one or more other compute nodes; a memory configured to store shared data that is shared with the one or more other compute nodes; and a processor configured to: determine an expected computational load for processing a computational model for input data; obtain a contributable computational load of the compute node and the one or more other compute nodes; and select a master node to distribute the determined expected computational load based on the obtained contributable computational load. Consequently, learning and inference can be performed efficiently on-device.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 28, 2023
    Assignee: LG ELECTRONICS INC.
    Inventors: Byoungjoo Lee, Jemin Woo, Jinjong Lee, Jungsig Jun
  • Publication number: 20200250509
    Abstract: The present disclosure relates to an artificial intelligence chip for processing computations for machine learning models that provides a compute node and a method of processing a computational model using a plurality of compute nodes in parallel. In some embodiments, the compute node, comprises: a communication interface configured to communicate with one or more other compute nodes; a memory configured to store shared data that is shared with the one or more other compute nodes; and a processor configured to: determine an expected computational load for processing a computational model for input data; obtain a contributable computational load of the compute node and the one or more other compute nodes; and select a master node to distribute the determined expected computational load based on the obtained contributable computational load. Consequently, learning and inference can be performed efficiently on-device.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 6, 2020
    Applicant: LG ELECTRONICS INC.
    Inventors: Byoungjoo LEE, Jemin WOO, Jinjong LEE, Jungsig JUN
  • Patent number: 6229560
    Abstract: An apparatus and method for determining co-channel interference in a DTV system is disclosed including a first comb filter filtering the received digital data including a data field signal; a pattern generating unit generating a reference sync signal from the data field signal; a second comb filter filtering the reference sync signal; a selection unit receiving either the digital data that passed or have not passed the first comb filter to output one of the data in response to a selection signal; a determination unit determining the presence of a co-channel interference; a first counting unit counting up/down a counted value in response to an output signal of the determination unit; and a second counting unit counting the reliability of the counted value output from the first counting unit, and providing the selection signal to the selection unit.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: May 8, 2001
    Assignee: LG Electronics Inc.
    Inventor: Jungsig Jun