Patents by Inventor Jung Tae Jeong

Jung Tae Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9721904
    Abstract: A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. Edge portions of the conductive elastic plate may be inserted into the trenches of the conductive guard rails and supported by the conductive guard rails by a force trying to stretch by the elastic restoring force of the wing portions of the conductive elastic plate.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventors: Seung Ho Kim, Soo Won Kang, Jung Tae Jeong
  • Patent number: 9699907
    Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 4, 2017
    Assignee: SK hynix Inc.
    Inventor: Jung Tae Jeong
  • Publication number: 20170162515
    Abstract: A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. Edge portions of the conductive elastic plate may be inserted into the trenches of the conductive guard rails and supported by the conductive guard rails by a force trying to stretch by the elastic restoring force of the wing portions of the conductive elastic plate.
    Type: Application
    Filed: March 24, 2016
    Publication date: June 8, 2017
    Inventors: Seung Ho KIM, Soo Won KANG, Jung Tae JEONG
  • Publication number: 20170148774
    Abstract: Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.
    Type: Application
    Filed: February 3, 2017
    Publication date: May 25, 2017
    Inventor: Jung Tae JEONG
  • Patent number: 9620492
    Abstract: A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 11, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jung Tae Jeong
  • Patent number: 9601469
    Abstract: Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 21, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jung Tae Jeong
  • Patent number: 9478515
    Abstract: A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 25, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jung Tae Jeong
  • Publication number: 20160307867
    Abstract: A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.
    Type: Application
    Filed: August 20, 2015
    Publication date: October 20, 2016
    Inventor: Jung Tae JEONG
  • Publication number: 20160295698
    Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.
    Type: Application
    Filed: July 30, 2015
    Publication date: October 6, 2016
    Inventor: Jung Tae JEONG
  • Publication number: 20160225743
    Abstract: A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.
    Type: Application
    Filed: June 3, 2015
    Publication date: August 4, 2016
    Inventor: Jung Tae JEONG
  • Publication number: 20160079210
    Abstract: A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Jung Tae JEONG, Il Hwan CHO
  • Patent number: 9275968
    Abstract: A flip chip package includes a chip having a surface, main bumps disposed on a first region of the surface of the chip, dummy bumps disposed on a second region of the surface of the chip, a substrate having a surface, dams disposed on the surface of the substrate, connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps, and adhesion patterns attaching the dummy bumps to respective ones of the dams.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 1, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jung Tae Jeong, Si Eon Kim, Jong Woo Ahn
  • Patent number: 9230915
    Abstract: A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jung Tae Jeong, Il Hwan Cho
  • Publication number: 20150348930
    Abstract: A flip chip package includes a chip having a surface, main bumps disposed on a first region of the surface of the chip, dummy bumps disposed on a second region of the surface of the chip, a substrate having a surface, dams disposed on the surface of the substrate, connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps, and adhesion patterns attaching the dummy bumps to respective ones of the dams.
    Type: Application
    Filed: October 16, 2014
    Publication date: December 3, 2015
    Inventors: Jung Tae JEONG, Si Eon KIM, Jong Woo AHN
  • Publication number: 20150179618
    Abstract: Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.
    Type: Application
    Filed: April 16, 2014
    Publication date: June 25, 2015
    Applicant: SK HYNIX INC.
    Inventor: Jung Tae JEONG
  • Publication number: 20140054772
    Abstract: A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.
    Type: Application
    Filed: December 18, 2012
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Jung Tae Jeong, Il Hwan Cho
  • Patent number: 8304879
    Abstract: A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Da Un Nah, Jae Myun Kim, Tae Hoon Kim, Jung Tae Jeong, Bok Gyu Min, Ki Bum Kim
  • Publication number: 20110108995
    Abstract: A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.
    Type: Application
    Filed: June 21, 2010
    Publication date: May 12, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Da Un NAH, Jae Myun KIM, Tae Hoon KIM, Jung Tae JEONG, Bok Gyu MIN, Ki Bum KIM