Patents by Inventor Jung Tang Chiang

Jung Tang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9161375
    Abstract: A method for sharing access to a wireless LAN access point is applicable between a target client device and a host device which is coupled to the wireless LAN access point, and includes the steps of: configuring the host device to send an invite request to the target client device, configuring the host device to receive an invite response sent by the target client device, and configuring the host device to exchange connection information with the target client device, such that the target client device may connect to the wireless LAN access point according to the connection information.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: October 13, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Zin-How Yang, Jung-Tang Chiang
  • Publication number: 20120265861
    Abstract: A method for sharing access to a wireless LAN access point is applicable between a target client device and a host device which is coupled to the wireless LAN access point, and includes the steps of: configuring the host device to send an invite request to the target client device, configuring the host device to receive an invite response sent by the target client device, and configuring the host device to exchange connection information with the target client device, such that the target client device may connect to the wireless LAN access point according to the connection information.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 18, 2012
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Zin-How Yang, Jung-Tang Chiang
  • Patent number: 7895402
    Abstract: A deinterleaving device includes a memory space, the memory space being divided into a plurality of N segments with different lengths respectively. A method of accessing data in a deinterleaving device, the method including performing the following steps during a first time cycle: reading first read data from a first address of a first segment; reading second read data from a first address of a second segment, and writing first write data into the first address of the second segment; reading third read data from a first address of a third segment, and writing second write data into the first address of the third segment; repeating the above reading and writing steps until reading Nth read data from a first address of an Nth segment, and writing N?1th write data into the first address of the Nth segment; writing Nth write data into the first address of the first segment.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Li Lee, Jung-Tang Chiang, Meng-Han Hsieh
  • Patent number: 7738580
    Abstract: A quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoding apparatus and the related method that receives and decodes a QAM signal. The QAM-TCM decoding apparatus includes an in-phase least significant bit (LSB) decoding path, which includes a in-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to an in-phase component of the QAM signal, a quadrature-phase LSB decoding path, which includes a quadrature-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to a quadrature-phase component of the QAM signal, and a most significant bit (MSB) decoding path for executing a decoding procedure on MSB portions corresponding to the in-phase or the quadrature-phase of the QAM signal.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 15, 2010
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jung-Tang Chiang, Hou-Wei Lin
  • Patent number: 7720165
    Abstract: A demapper, applied to a quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoder, for generating more significant bits of a QAM signal according to the QAM signal and at least a less significant bit of the QAM signal is disclosed. The demapper includes a shifter for shifting the QAM signal to generate a shifted signal; a threshold value comparing and mapping unit for outputting at least a more-significant-bit buffered value; a sign bit decider for determining a sign value corresponding to the shifted signal; a multiplexer for generating a first more-significant-bit estimation and a second more-significant-bit estimation; and an operating unit for determining a third more-significant-bit estimation and a fourth more-significant-bit estimation.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 18, 2010
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Li Lee, Jung-Tang Chiang
  • Patent number: 7590928
    Abstract: A Viterbi decoding apparatus and a method thereof are disclosed. According to each partial surviving path formed by the decision information of every k continuous symbols of a symbol sequence, the apparatus can write its start trellis state and corresponding partial decoded information into a memory unit. On the other hand, the apparatus performs traceback reads and decode reads according to the content of the memory unit, thereby decoding a decoded information sequence corresponding to the symbol sequence. In this manner, memory space can be saved and the operating speed for traceback/decode reads need no acceleration. Thus, hardware cost and design complexity can be reduced simultaneously.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: September 15, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jung Tang Chiang
  • Publication number: 20080109626
    Abstract: A deinterleaving device includes a memory space, the memory space being divided into a plurality of N segments with different lengths respectively. A method of accessing data in a deinterleaving device, the method including performing the following steps during a first time cycle: reading first read data from a first address of a first segment; reading second read data from a first address of a second segment, and writing first write data into the first address of the second segment; reading third read data from a first address of a third segment, and writing second write data into the first address of the third segment; repeating the above reading and writing steps until reading Nth read data from a first address of an Nth segment, and writing N?1th write data into the first address of the Nth segment; writing Nth write data into the first address of the first segment.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 8, 2008
    Inventors: Kai-Li Lee, Jung-Tang Chiang, Meng-Han Hsieh
  • Publication number: 20070110187
    Abstract: A demapper, applied to a quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoder, for generating more significant bits of a QAM signal according to the QAM signal and at least a less significant bit of the QAM signal is disclosed. The demapper includes a shifter for shifting the QAM signal to generate a shifted signal; a threshold value comparing and mapping unit for outputting at least a more-significant-bit buffered value; a sign bit decider for determining a sign value corresponding to the shifted signal; a multiplexer for generating a first more-significant-bit estimation and a second more-significant-bit estimation; and an operating unit for determining a third more-significant-bit estimation and a fourth more-significant-bit estimation.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 17, 2007
    Inventors: Kai-Li Lee, Jung-Tang Chiang
  • Publication number: 20060274845
    Abstract: A quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoding apparatus and the related method that receives and decodes a QAM signal. The QAM-TCM decoding apparatus includes an in-phase least significant bit (LSB) decoding path, which includes a in-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to an in-phase component of the QAM signal, a quadrature-phase LSB decoding path, which includes a quadrature-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to a quadrature-phase component of the QAM signal, and a most significant bit (MSB) decoding path for executing a decoding procedure on MSB portions corresponding to the in-phase or the quadrature-phase of the QAM signal. In doing so, the apparatus and method reduces the complexity of the decoding calculation.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 7, 2006
    Inventors: Jung-Tang Chiang, Hou-Wei Lin
  • Publication number: 20060245526
    Abstract: A Viterbi decoding apparatus and a method thereof are disclosed. According to each partial surviving path formed by the decision information of every k continuous symbols of a symbol sequence, the apparatus can write its start trellis state and corresponding partial decoded information into a memory unit. On the other hand, the apparatus performs traceback reads and decode reads according to the content of the memory unit, thereby decoding a decoded information sequence corresponding to the symbol sequence. In this manner, memory space can be saved and the operating speed for traceback/decode reads need no acceleration. Thus, hardware cost and design complexity can be reduced simultaneously.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 2, 2006
    Inventor: Jung Tang Chiang