Patents by Inventor Jung-Tang WU

Jung-Tang WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391534
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Publication number: 20210336130
    Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.
    Type: Application
    Filed: February 5, 2021
    Publication date: October 28, 2021
    Inventors: Yu-Jen CHIEN, Jung-Tang WU, Szu-Hua WU, Chin-Szu LEE, Meng-Yu WU
  • Publication number: 20210296571
    Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Jung-Tang Wu, Yu-Jen Chien, Szu-Hua Wu, Chin-Szu Lee, Yao-Shien Huang
  • Publication number: 20210288249
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang WU, Jui-Hung HO, Chin-Szu LEE, Meng-Yu WU, Szu-Hua WU
  • Patent number: 11107980
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Publication number: 20210249591
    Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Jung-Tang Wu, Meng Yu Wu, Szu-Hua Wu, Chin-Szu Lee
  • Patent number: 11031236
    Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang Wu, Yu-Jen Chien, Szu-Hua Wu, Chin-Szu Lee, Yao-Shien Huang
  • Patent number: 11024801
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 1, 2021
    Inventors: Jung-Tang Wu, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Patent number: 11022437
    Abstract: A leveling sensor, a load port including a leveling sensor, and a method of leveling a load port using a load port are disclosed. In an embodiment, a sensor includes an accelerometer configured to detect leveling and vibration of a load port and produce a plurality of data; a plurality of indicator lights configured to display a level measurement and a level direction based on the leveling of the load port; a processor configured to process the data produced by the accelerometer; and a wired connection configured to connect the processor to an external device.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Wang, Jung-Tang Wu, Chin-Szu Lee, Hua-Sheng Chiu
  • Patent number: 10991876
    Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee
  • Publication number: 20210119120
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang WU, Szu-Ping TUNG, Szu-Hua WU, Shing-Chyang PAN, Meng-Yu WU
  • Publication number: 20210098248
    Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Jung-Tang Wu, Yu-Jen Chien, Szu-Hua Wu, Chin-Szu Lee, Yao-Shien Huang
  • Patent number: 10879114
    Abstract: A conductive fill is provided in an opening of an interconnect layer. A seed layer is formed, a portion of which is then oxidized. The oxygen is removed in a treatment process and the surface of the de-oxidized seed layer is hydrolyzed to form a hydroxyl sublayer and moisturized. The conductive fill is formed over the hydroxyl sublayer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Patent number: 10872815
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Patent number: 10862026
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Publication number: 20200357693
    Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang WU, Pao-Sheng CHEN, Pei-Hsuan LEE, Szu-Hua WU, Chih-Chien CHI
  • Publication number: 20200258777
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Patent number: 10727118
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Pao-Sheng Chen, Pei-Hsuan Lee, Szu-Hua Wu, Chih-Chien Chi
  • Publication number: 20200149886
    Abstract: A leveling sensor, a load port including a leveling sensor, and a method of leveling a load port using a load port are disclosed. In an embodiment, a sensor includes an accelerometer configured to detect leveling and vibration of a load port and produce a plurality of data; a plurality of indicator lights configured to display a level measurement and a level direction based on the leveling of the load port; a processor configured to process the data produced by the accelerometer; and a wired connection configured to connect the processor to an external device.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yi-Lin Wang, Jung-Tang Wu, Chin-Szu Lee, Hua-Sheng Chiu
  • Publication number: 20200152864
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang WU, Szu-Ping TUNG, Szu-Hua WU, Shing-Chyang PAN, Meng-Yu WU