Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: The present invention relates to a power management method for portable computers with a wireless device and detects the electric power source of a portable computer through a power source detection circuit during the operation of portable computer. In addition, any one of the following is dynamically changed: the supporting rate of the connection interface between a wireless device and the portable computer, the data rate between the AP (Access Point) and the wireless device. Moreover, the invention provides a plurality of input methods for triggering the power saving modes of the portable computer to achieve the object of reducing power consumption.

Abstract: An electronic device holder for a bicycle, which consists of a fixed base, a belt body, a support unit, a left clamp and a right clamp, wherein the belt is passed through the fixed base and fixed on a bicycle handle, a first connector is set on one side of the fixed base, the first connector is connected to a second connector of the support unit, at least a chute is set on the left side and the right side of the support unit respectively that the left clamp and the right clamp may be slipped laterally along the chute, to thereby fixedly clamp a portable electronic device and achieve the purpose of using the electronic device conveniently when riding.

Abstract: A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.

Abstract: A method for determining a buffer size of devices in an embedded system is disclosed. A buffer fill time (BFT) and a request response time (RRT) are determined. Next, a media data rate (MDR) and a number of bus masters (NBM) are calculated. Finally, a lowest buffer size of a device is determined according to the BFT, the MDR and NBM of the system.

Abstract: A method for determining a buffer size of devices in an embedded system is disclosed. A buffer fill time (BFT) and a request response time (RRT) are determined. Next, a media data rate (MDR) and a number of bus masters (NBM) are calculated. Finally, a lowest buffer size of a device is determined according to the BFT, the MDR and NBM of the system.

Abstract: The present invention relates to an embedded system and method, and in particular relates to an embedded system with a bus and an arbitration method. An arbitration method is applied in an embedded system that comprises a plurality of devices, a bus and an arbiter. Each device comprises a buffer and a time-to-death value. The arbiter chooses one device to access data through the bus according to the plurality of TTD values. The arbitration method comprises: sending a plurality of request signals to the arbiter; choosing one device to access data through the bus according to the plurality of TTD values, wherein the chosen device with a minimum TTD value is chosen; increasing the TTD value of the chosen device when the chosen device is accessing data through the bus; choosing another device to access data through the bus when the TTD value of another device becomes minimum.

Abstract: A data transmission method and apparatus in a communication system to avoid data buffer overrun by using a smaller data buffer. The communication system includes an AP (access point) and a host device connected to a wireless device with a USB interface circuit. The wireless device includes a data buffer for receiving data from the AP. The data rate between the AP and the wireless device decreases or increases based on a utilization of the data buffer to avoid errors.

Abstract: In network systems having a wireless medium, such as IEEE802.11e based networks, each frame of a station is classified as one of a plurality of traffic categories, and frames of some traffic categories have a higher transmission opportunity than frames of other traffic categories. Before a station transmits frames to the network media, a media access control circuit in the station performs an internal access to read the frames from a system memory of the station. While performing the internal access, the presented invention reads frames in an order corresponding to media accessing priorities assigned in traffic categories of those frames, such that hardware cost, complexity and layout area of the medium access control circuit are all reduced.

Abstract: A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.

Abstract: Method and related apparatus for realizing a two-port synchronous memory device with a single-port memory. Clock-triggered two-port synchronous memory device can synchronously receive reading and writing commands within a clock period to simultaneous execute these two commands, while a single port memory must execute a single reading and writing command sequentially. Since a single-port memory features a lower cost and a smaller layout area, the invention realizes a two-port synchronous memory device by making a single-port memory first execute one of the reading/writing commands and then the other command within a single clock period, such that the two commands are completed after a single clock period. Thus a two-port synchronous memory device can be realized with a single-port memory.

Abstract: Disclosed is an integrated PCI interface card, comprising a multi-functional IC chip, a first set of signal lines, a mono-functional IC chip, and a second set of signal lines. The multi-functional IC chip includes a plurality of functional circuits and an arbiter, and each of the first set of signal lines and the second set of signal lines includes the signal lines required in the PCI bus transactions. The first set of signal lines is arranged to couple the multi-functional IC chip to a PCI bus, and a request signal line, a grant signal line, and an initialization device select signal line of the second set of signal lines are arranged to couple the multi-functional IC chip and the mono-functional IC chip, while the other signal lines of the second set of signal lines are arranged to couple the mono-functional IC chip to the PCI bus.

Abstract: A real-time decryption system and method utilizing Content Addressable Memory (CAM) for synchronously comparing network addresses in wireless communications. First, a network address table and a decryption key table are provided, wherein the decryption key table comprises a plurality of decryption keys, and the network address table comprises a plurality of network addresses correspondingly. Thereafter, a packet is received, wherein the packet comprises a source address and a ciphertext. The source address is then compared with the network addresses, thus a decryption key from a location of the decryption key table can be obtained according to the network address if one network address matches the source address. At last, the ciphertext is decrypted with the decryption key to generate a plaintext.

Abstract: A synchronization element for converting an asynchronous pulse signal into a synchronous pulse signal with reference to a clock signal according to the invention. The synchronization element has four flip-flops consisting of a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop, two AND gates, an NAND gate and an inverter. The first flip-flop can capture the rising edges of an input signal. The second and third flip-flops can generate a pulse signal synchronous to the reference clock signal according to whether or not the first flip-flop is latched. The fourth flip-flop is used to reset the other flip-flops. The NAND and One of the two AND gates can generate appropriate control signals to control corresponding signals.

Abstract: A bottle holder for a bicycle includes a plate, two sleeves formed in the side edges of the plate, a top frame and a bottom frame each having two legs engaged in the sleeves respectively so as to form a frame for holding the bottle. The number of dents are formed in each of the sleeves and extended inward of the sleeves and engaged with the legs of the top frame and the bottom frame such that the frames are solidly secured to the sleeves of the plate.