Patents by Inventor Jung-Wang Lu

Jung-Wang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006157
    Abstract: Methods and systems for dry etching are disclosed. The methods and systems use a showerhead with a perforated plate. The perforated plate includes a primary solid zone having no holes; a first annular zone comprising a first plurality of holes with a first total hole area; a secondary solid zone having no holes; a second annular zone comprising a second plurality of holes with a second total hole area; a third annular zone comprising a third plurality of holes with a third total hole area; and a fourth annular zone comprising a fourth plurality of holes with a fourth total hole area. The third total hole area is greater than the first total hole area and less than the second total hole area, and the fourth total hole area is greater than the second total hole area. Dry etched wafers using these systems have improved edge uniformity and improved yield.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: Chien-Liang Chen, Shao-Chien Hsu, Jung-Wang Lu, Meng-Chang Wu
  • Patent number: 9882013
    Abstract: Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Wang Lu, Kuo Hui Chang, Mu-Tsang Lin
  • Publication number: 20170288032
    Abstract: Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Jung-Wang Lu, Kuo Hui Chang, Mu-Tsang Lin