Patents by Inventor Jung Won

Jung Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070220713
    Abstract: Provided are low-temperature formation methods of a perfectly oriented ZnO nanorod array and a new-type ZnO nanowall array having a new crystal growth rate, morphology, and orientation, from ZnO nanoparticles coated on a substrate. The method of forming the ZnO nanorod array includes synthesizing ZnO nanoparticles, coating on a substrate the ZnO nanoparticles serving both as a buffer layer and a seed layer, and growing the ZnO nanoparticles into crystals in a nutrient solution containing Zn nitrate, Zn acetate, or a derivative thereof, and hexamethylenetetramine. The method of forming the ZnO nanowall array includes synthesizing ZnO nanoparticles, coating on a substrate the ZnO nanoparticles serving both as a buffer layer and a seed layer, and growing the ZnO nanoparticles into crystals in a nutrient solution containing Zn acetate or its derivative and sodium citrate.
    Type: Application
    Filed: November 6, 2004
    Publication date: September 27, 2007
    Inventors: Jin Choy, Eue Jang, Jung Won
  • Publication number: 20070148520
    Abstract: Disclosed herein are a metal(III)-chromium-phosphate complex represented by a formula of M(III)xCr(HPO4)y(H2PO4)z and the use thereof. More particularly, disclosed are an organic/inorganic composite electrolyte membrane comprising said complex, an electrode comprising said complex, a membrane-electrode assembly (MEA) comprising said organic/inorganic composite electrolyte membrane and/or electrode, and a fuel cell comprising said membrane-electrode assembly.
    Type: Application
    Filed: December 26, 2006
    Publication date: June 28, 2007
    Inventors: Chong Shin, Jung Won, Bong Lee, Yong Park, Jae Chang, Dong Kim
  • Publication number: 20070026666
    Abstract: Provided is a method of forming a metal line of a semiconductor device. The method includes the following. A metal line is formed on a semiconductor substrate. An etch barrier layer is formed on the entire surface of the semiconductor substrate including the metal line. A low-k dielectric layer is formed on the etch barrier layer. The low-k dielectric layer is selectively removed to form a via hole using the etch barrier layer as an etch end point. Nitrogen gas is applied on the via hole to remove foreign substances formed during the forming of the via hole and simultaneously protect the side surface of the via hole.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 1, 2007
    Inventor: Jung Won