Patents by Inventor Jung Woon Shim

Jung Woon Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330771
    Abstract: A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 3, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jung Woon Shim
  • Publication number: 20160099063
    Abstract: A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings.
    Type: Application
    Filed: February 11, 2015
    Publication date: April 7, 2016
    Inventor: Jung Woon SHIM
  • Publication number: 20160093391
    Abstract: A semiconductor device may include a memory string coupled between a bit line and a common source line and configured to include a drain select transistor, memory cells, and a source select transistor. The drain select transistor may be configured to operate based on a voltage applied to a drain select line. The memory cells may be configured to operate based on a voltage applied to word lines. The source select transistor may be configured to operate based on a voltage applied to a source select line. The semiconductor device may include an operation circuit configured to perform a read operation or a verify operation of the memory cells. The operation circuit may be configured to apply a negative voltage to the common source line during the read operation or the verify operation.
    Type: Application
    Filed: February 12, 2015
    Publication date: March 31, 2016
    Inventor: Jung Woon SHIM
  • Patent number: 9236130
    Abstract: Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jung Woon Shim
  • Patent number: 9117540
    Abstract: A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral circuit so that the operating voltage being applied to the selection transistors is controlled to reduce a potential level of a channel of the memory cell strings during the read operation or the verify operation.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 25, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jung Woon Shim
  • Patent number: 9082488
    Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 14, 2015
    Assignee: SK HYNIX INC.
    Inventors: Jung Woon Shim, Sung Jae Chung, Jin Gu Kim, Dong Hwan Lee, Seung Won Kim, Su Min Yi
  • Publication number: 20150155040
    Abstract: Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 4, 2015
    Applicant: SK HYNIX INC.
    Inventor: Jung Woon SHIM
  • Patent number: 9042176
    Abstract: The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing a program operation on selected memory cells by applying a program pulse to the selected memory cells.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: May 26, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jung Woon Shim
  • Publication number: 20140347921
    Abstract: A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral circuit so that the operating voltage being applied to the selection transistors is controlled to reduce a potential level of a channel of the memory cell strings during the read operation or the verify operation.
    Type: Application
    Filed: August 20, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventor: Jung Woon SHIM
  • Publication number: 20140169097
    Abstract: The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing a program operation on selected memory cells by applying a program pulse to the selected memory cells.
    Type: Application
    Filed: July 23, 2013
    Publication date: June 19, 2014
    Applicant: SK hynix Inc.
    Inventor: Jung Woon SHIM
  • Publication number: 20140063968
    Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventors: Jung Woon Shim, Sung Jae Chung, Jin Gu Kim, Dong Hwan Lee, Seung Won Kim, Su Min Yi