Patents by Inventor Jung Yong CHAE

Jung Yong CHAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411248
    Abstract: A semiconductor device may include a via hole, a first electrode, a second electrode and a first protecting insulation layer. The via hole may be formed to penetrate a substrate. The first electrode may include an electrode segment formed on a surface of the via hole. The second electrode may be formed on the first electrode along the surface of the via hole. The second electrode may include two ends that are positioned below a surface of the substrate. The first protecting insulation layer may be formed on the second electrode along the surface of the via hole. The first protecting insulation layer may include both ends that upwardly protrude from the both ends of the second electrode.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Jung Yong CHAE, Jin Hee CHO
  • Publication number: 20230411249
    Abstract: A semiconductor device may include a via hole, a first electrode, a second electrode and a first protecting insulation layer. The via hole may be formed to penetrate a substrate. The first electrode may include an electrode segment formed on a surface of the via hole. The second electrode may be formed on the first electrode along the surface of the via hole. The second electrode may include two ends that are positioned below a surface of the substrate. The first protecting insulation layer may be formed on the second electrode along the surface of the via hole. The first protecting insulation layer may include both ends that upwardly protrude from the both ends of the second electrode.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Jung Yong CHAE, Jin Hee CHO
  • Patent number: 11769711
    Abstract: A semiconductor device may include a via hole, a first electrode, a second electrode and a first protecting insulation layer. The via hole may be formed to penetrate a substrate. The first electrode may include an electrode segment formed on a surface of the via hole. The second electrode may be formed on the first electrode along the surface of the via hole. The second electrode may include two ends that are positioned below a surface of the substrate. The first protecting insulation layer may be formed on the second electrode along the surface of the via hole. The first protecting insulation layer may include both ends that upwardly protrude from the both ends of the second electrode.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: September 26, 2023
    Assignee: SK HYNIX INC.
    Inventors: Jung Yong Chae, Jin Hee Cho
  • Publication number: 20220199493
    Abstract: A semiconductor device may include a via hole, a first electrode, a second electrode and a first protecting insulation layer. The via hole may be formed to penetrate a substrate. The first electrode may include an electrode segment formed on a surface of the via hole. The second electrode may be formed on the first electrode along the surface of the via hole. The second electrode may include two ends that are positioned below a surface of the substrate. The first protecting insulation layer may be formed on the second electrode along the surface of the via hole. The first protecting insulation layer may include both ends that upwardly protrude from the both ends of the second electrode.
    Type: Application
    Filed: March 31, 2021
    Publication date: June 23, 2022
    Inventors: Jung Yong CHAE, Jin Hee CHO
  • Publication number: 20220013562
    Abstract: An image sensing device is provided to include a semiconductor substrate having a first surface and a second surface and including different portions for a pixel region including pixel structures and a pad region, a first pad metal layer formed over the first surface of the semiconductor substrate and located in the pad region, an anti-reflection layer formed over a first portion of the first pad metal layer to contact a top surface of the first pad metal layer, and a pad passivation layer formed over the first pad metal layer and the anti-reflection layer. A second portion of the first pad metal layer is provided as a pad open region formed to expose the top surface of the first pad metal layer and an interface between the first pad metal layer and the anti-reflection layer are structured not to be exposed to an outside.
    Type: Application
    Filed: February 23, 2021
    Publication date: January 13, 2022
    Inventors: Yun Hui YANG, Jung Yong CHAE