Abstract: A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information to a mode register of the corresponding memory device, and controlling resistances of ODT resistors of the signal lines in the memory devices in response to the address/command or data termination information and termination addresses. When only one of the memory devices is activated, ODT resistors of the activated memory device are set to a first resistance. When all the memory devices are activated, ODT resistors of the memory devices are set to a second resistance.

Abstract: A memory device includes a temperature sensor configured to generate a temperature detection signal responsive to a temperature of the memory device and a self-refresh control circuit configured to control a refresh of the memory device responsive to the temperature detection signal. The device further includes a temperature-detection-error sensing circuit configured to assert a temperature-detection-error signal responsive to an error in the temperature detection signal. The temperature-detection-error sensing circuit may be configured to provide the asserted temperature-detection-error signal at a temperature-detection-error sensing pad configured to be coupled to an external device and/or the device may further include a temperature sensor control circuit configured to control the temperature detection signal responsive to the temperature-detection-error signal. Related operating and testing methods may be provided.

Abstract: A semiconductor memory device includes a mode register, an additional function executer, and an additional function controller. The mode register activates an additional function control signal when a mode register set code indicates that an additional function is to be executed concurrently with a refresh operation. The additional function controller controls the additional function executer to carry out the additional function concurrently with the refresh operation when the additional function control signal is activated.

Abstract: Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

Abstract: A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.

Abstract: A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

Abstract: A memory device includes a temperature sensor configured to generate a temperature detection signal responsive to a temperature of the memory device and a self-refresh control circuit configured to control a refresh of the memory device responsive to the temperature detection signal. The device further includes a temperature-detection-error sensing circuit configured to assert a temperature-detection-error signal responsive to an error in the temperature detection signal. The temperature-detection-error sensing circuit may be configured to provide the asserted temperature-detection-error signal at a temperature-detection-error sensing pad configured to be coupled to an external device and/or the device may further include a temperature sensor control circuit configured to control the temperature detection signal responsive to the temperature-detection-error signal. Related operating and testing methods may be provided.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

Abstract: The present invention discloses a semiconductor memory device and a method of generating a block selection signal for the semiconductor memory device. The semiconductor memory device includes 2n groups comprised of m memory cell array blocks and each of the memory cell array blocks has (2k+a) word lines. The semiconductor memory device further includes a first block selection signal generating circuit for generating first block selection signals for selecting one group of the 2n groups by decoding a n-bit row address, a second block selection signal generating circuit for generating second block selection signals for selecting one memory cell array block in every group by decoding a l-bit row address, and a third block selection signal generating circuit for generating third block selection signals for selecting one memory cell array block out of (m×2n) memory cell array blocks by receiving the first block selection signals and the second block selection signals.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: The present invention discloses a semiconductor memory device and a method of generating a block selection signal for the semiconductor memory device. The semiconductor memory device includes 2n groups comprised of m memory cell array blocks and each of the memory cell array blocks has (2k+a) word lines. The semiconductor memory device further includes a first block selection signal generating circuit for generating first block selection signals for selecting one group of the 2n groups by decoding a n-bit row address, a second block selection signal generating circuit for generating second block selection signals for selecting one memory cell array block in every group by decoding a l-bit row address, and a third block selection signal generating circuit for generating third block selection signals for selecting one memory cell array block out of (m×2n) memory cell array blocks by receiving the first block selection signals and the second block selection signals.