Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer having a connection pad; and a resist layer formed on the insulating layer and provided with an opening so that the connection pad is exposed, wherein a wall surface of an opening of the resist layer may have at least one protrusion.

Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.

Abstract: A printed circuit board includes an insulating layer; a metal pad formed on the insulating layer; a surface treatment layer formed on the metal pad; a solder layer formed on the surface treatment layer and the insulating layer; and an intermetallic compound layer formed between the solder layer and the surface treatment layer. Further, a printed circuit board may include an insulating layer; a metal seed layer formed on the insulating layer; a metal pad formed on the metal seed layer; a surface treatment layer formed on the metal pad and the metal seed layer; a solder layer formed on the surface treatment layer of the metal pad and the surface treatment layer of the metal seed layer; and an intermetallic compound layer formed between the solder layer and the surface treatment layer.

Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.

Abstract: A circuit board includes a circuit pattern formed on a substrate, a first solder resist layer formed on the circuit pattern, an electroless plating layer formed on the circuit pattern on which the first solder resist layer is opened, and a second solder resist layer formed on the first solder resist layer, and a method for manufacturing the same. According to certain embodiments, it is possible to cover a portion which has vulnerable plating quality due to solder resist residue or insufficient wetting around an edge of an existing solder resist layer by including an additional solder resist layer on a surface-treated plating layer. Further, it is possible to protect an undercut portion under the solder resist layer by forming the additional solder resist layer.

Abstract: Disclosed herein are an electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein each of the electroless nickel, palladium, and gold plated coatings has a thickness of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a copper pad surface roughness-treated to have a surface roughness of 0.1 to 1.0 ?m pitch period; and an electroless surface treatment plating layer formed on the copper pad. According to the present invention, when the copper pad has a surface roughness of a predetermined pitch period, the electroless surface treatment plating layer formed on the copper pad also has a surface roughness of the predetermined pitch period, thereby having an effect of widening a surface area and improving workability at the time of a wire bonding process for connection with an external device.