Abstract: The present application discloses a flow speed detection circuit and a related chip and flow meter. The flow speed detection circuit includes: a transmitter, configured to provide a front signal and a main signal to a first transducer, wherein the first transducer transforms the front signal and the main signal into a transduced signal to a second transducer, the second transducer transforms the transduced signal into a receiving front signal and a receiving main signal to a receiver; and the receiver includes: a front signal detection circuit, configured to enable the main signal processing circuit after the receiving front signal; and the main signal processing circuit, configured to determine the flow speed based on the receiving main signal after being enabled.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer; the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The application discloses a signal generation circuit (100), configured to generate a transmission signal to trigger a first transducer to generate a first transducer output signal; the signal generation circuit includes: a signal generation unit (106), configured to generate an output signal; and a transmitter (104), coupled to the signal generation unit, wherein the transmitter is configured to convert the output signal into the transmission signal; wherein the transmission signal includes a data signal and a compensation signal, the data signal includes at least one first pulse wave, the compensation signal includes at least one second pulse wave, the first pulse wave and the second pulse wave have opposite phases, and the first pulse wave has an other waveform parameter different from an other waveform parameter of the second pulse wave. The present application further provides a related chip, a flow meter and a method.

Abstract: A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

Abstract: The present application discloses a flow speed detection circuit and a related chip and flow meter. Said flow speed detection circuit is coupled to a first transducer and a second transducer that are external to the flow speed detection circuit, wherein the flow speed detection circuit includes: a transmitter, configured to provide a front signal and a main signal to the first transducer, wherein the first transducer transforms the front signal and the main signal into a transduced signal to the second transducer, the second transducer transforms the transduced signal into a receiving front signal and a receiving main signal to a receiver; and the receiver includes: a front signal detection circuit, configured to enable the main signal processing circuit after the receiving front signal; and the main signal processing circuit, configured to determine the flow speed based on the receiving main signal after being enabled.

Abstract: The application discloses a time-of-flight (TOF) generating circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer are arranged in a pipeline (120) filled with fluid. The TOF generating circuit includes a first transmitter (106) and a first receiver (108), a second transmitter (110) and a second receiver (112), a signal generating circuit (114), a correlation circuit (116), and a processing circuit (118). Under different ambient factors, the signal generating circuit generates, respectively, a first signal and a second signal, which are received by the second receiver and the first receiver to generate a first receiving signal (RS1) and a second receiving signal (RS2), respectively. The correlation circuit performs a correlation operation to generate a first correlation signal (CS1). The processing circuit generates the TOF variation according at least to the first correlation signal (118).

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer; the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The present application discloses a signal processing circuit, configured to process a transducer output signal, wherein the transducer output signal is generated when the transducer is triggered by a transducer input signal at a first time point, and the signal processing circuit includes: a receiver, configured to receive the transducer output signal and convert the received transducer output signal into a receiving signal; and a signal truncating module (106), configured to divide the receiving signal into a first portion and a second portion, and generate a truncated receiving signal according to the first portion and the second portion of the receiving signal, the first portion and the second portion of the receiving signal continue and do not overlap in a time domain, and the truncated receiving signal also has a first portion and a second portion corresponding to the first portion and the second portion of the receiving signal.

Abstract: The application discloses a signal generation circuit (100), configured to generate a transmission signal to trigger a first transducer to generate a first transducer output signal; the signal generation circuit includes: a signal generation unit (106), configured to generate an output signal; and a transmitter (104), coupled to the signal generation unit, wherein the transmitter is configured to convert the output signal into the transmission signal; wherein the transmission signal includes a data signal and a compensation signal, the data signal includes at least one first pulse wave, the compensation signal includes at least one second pulse wave, the first pulse wave and the second pulse wave have opposite phases, and the first pulse wave has an other waveform parameter different from an other waveform parameter of the second pulse wave. The present application further provides a related chip, a flow meter and a method.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.