Patents by Inventor Jung-Yu Tsai

Jung-Yu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8414659
    Abstract: An antibacterial composition including silver nano particles, a protective agent and water is provided. The molar ratio of the silver nano particles to the protective agent is 1:0.995-1 and the protective agent is selected from a group consisting of MCl, MBr, MI, MS2O3 and NH4OH, in which M represents an element of group IA or IIA. Furthermore, two methods of fabricating an antibacterial textile are also provided.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: April 9, 2013
    Assignee: Taiwan Textile Research Institute
    Inventor: Jung-Yu Tsai
  • Publication number: 20100112884
    Abstract: An antibacterial composition including silver nano particles, a protective agent and water is provided. The molar ratio of the silver nano particles to the protective agent is 1:0.995-1 and the protective agent is selected from a group consisting of MCl, MBr, MI, MS2O3 and NH4OH, in which M represents an element of group IA or IIA. Furthermore, two methods of fabricating an antibacterial textile are also provided.
    Type: Application
    Filed: December 9, 2008
    Publication date: May 6, 2010
    Applicant: TAIWAN TEXTILE RESEARCH INSTITUTE
    Inventor: Jung-Yu Tsai
  • Patent number: 6292393
    Abstract: A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: September 18, 2001
    Assignee: Winbond Electronics Corp.
    Inventors: Jung-Yu Tsai, Chih-Mu Huang, Chi-Hung Kao, Chuan-Jane Chao
  • Patent number: 6200859
    Abstract: A split-gate flash memory is formed by a method described in the following steps. A tunnelling oxide layer, a first conductive layer, and a hard mask layer are formed on a substrate in sequence. A drain opening and a floating gate opening are formed on the hard mask layer by defining the hard mask layer in order to expose the first conductive layer. A first polyoxide layer and a second polyoxide layer are formed on the first conductive layer exposed by the drain opening and the floating gate opening, respectively. The first polyoxide layer and the first conductive layer beneath the first polyoxide layer are removed to expose the substrate in the drain opening. A drain region is formed in the substrate in the drain opening. The hard mask layer is removed, and the first conductive layer is etched into a floating gate using the second polyoxide layer as a mask. A split-gate oxide layer and a second conductive layer are formed on the resulting structure in sequence.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: March 13, 2001
    Assignee: Winbond Electronics Corp.
    Inventors: Chih-Mu Huang, Jung-Yu Tsai, Shing-Hwa Renn, Shu-Huei Lin