Patents by Inventor Jung-Yueh Chang

Jung-Yueh Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138018
    Abstract: A user equipment assistance information (UAI) negotiation method, for a user equipment (UE) of mobile communication includes receiving a first OtherConfig element of an RRC reconfiguration message comprising a plurality of configuration parameters with SETUP values from a network terminal; sending a first UAI including a first value of a first configuration parameter of the configuration parameters to the network terminal; and receiving a first RRC reconfiguration message corresponding to the first UAI from the network terminal.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 25, 2024
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Hung-Yueh Chen, Yu-Lun Chang, Byeng Hyun Kim, JUNG SHUP SHIN, Hung-Yuan Yang, Jun-Jie Su, Kyung Hyun Ahn
  • Publication number: 20240129766
    Abstract: A throttle control method for a mobile device include collecting input data, generating a first set of user experience indices according to the input data, and checking whether a user experience index of the first set of user experience indices satisfies a UEI threshold. The input data includes common information data, current configuration data and a plurality of throttle control parameters. Each user experience index of the first set of user experience indices is corresponding to at least one of throttle control parameter of the plurality of throttle control parameters.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 18, 2024
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Hung-Yueh Chen, Byeng Hyun Kim, JUNG SHUP SHIN, Shih-Hsin Chen, Chih-Chieh Lai, Chung-Pi Lee, JUNGWOO LEE, Yu-Lun Chang
  • Patent number: 6737745
    Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
  • Patent number: 6734093
    Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
  • Publication number: 20030017691
    Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.
    Type: Application
    Filed: September 18, 2002
    Publication date: January 23, 2003
    Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
  • Patent number: 6486051
    Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: November 26, 2002
    Assignee: Intel Corporation
    Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
  • Patent number: 6396326
    Abstract: A driver having a cascode stage with a common gate transistor that provides an output transmit signal at a driver output node. A protection circuit includes a resistor coupled to bias a gate of the common gate transistor to a clamp voltage. The resistor has a resistance value at least large enough to allow the gate voltage to follow some of a transition in the driver output node voltage when the driver is not transmitting. The resistance value may also be selected to delay the gate voltage from returning to the clamp voltage following the transition, so that the voltage between the gate and a source of the common gate transistor does not reach a level that can damage the common gate transistor.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 28, 2002
    Assignee: Intel Corporation
    Inventor: Jung-Yueh Chang
  • Patent number: RE41355
    Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang