Abstract: An identifier for identifying a source driver of a chip-on-glass liquid crystal display and an identifying method thereof are provided. The identifier includes a comparator for receiving a chip identity and a target identity, and generates a triggering signal to activate the source driver if the chip identity coincides with the target identity.

Abstract: A display implemented with a unique circuit arrangement. The display includes a glass substrate, a plurality of serial-connected source drivers and at least one gate driver. The source drivers and the at least one gate driver are disposed on the glass substrate using, for example, chip-on-glass technology. The display further includes at least one flexible connector, such as a flexible printed circuit board. Each of the at least one flexible connector corresponds to a selected one of the source drivers. The selected one of the source drivers is configured to receive image data and control information from the corresponded flexible connector, and convey the image data and the control information to at least one neighboring source driver.

Abstract: A liquid crystal display is disclosed, which includes a panel having an array of pixels, a timing controller outputting image data and source control signals, a series of source drivers and a gate driver. One of the source drivers is selected to generate gate control signals by reference to at least one of the source control signals and transmitted to the gate driver. Thus, the gate driver along with the source drivers can drive the panel pixels.

Abstract: A method for transmitting control signals of a liquid crystal display is provided. The LCD includes a timing controller. The method packs the control signals of the timing controller into a control packet which comprises a header field and a control item having a control field and a data field. The header field indicates the start of the control packet, the control field records a type of an event, and the data field records a parameter of the event. The control packet is transmitted on one or a limited number of transmission lines.

Abstract: A digital to analog converter of the source driver includes a gamma voltage generator and a data decoder. The gamma voltage generator receives a gamma code to generate an analog gamma voltage. The gamma voltage includes a register, a reference decoder, and a calibrator. The register stores the gamma code. The reference decoder converts the gamma code from the register into the analog gamma voltage. The calibrator, receiving a reference gamma voltage in a calibration mode, includes a comparator and a counter, in which the counter tunes the gamma code according to the control signal generated by the comparator comparing the analog gamma voltage and the reference gamma voltage. The data decoder receives digital pixel data and selects one gamma voltage as a driving voltage based on the digital pixel data.

Abstract: The present invention discloses a shift register circuit comprising a plurality of shift register units and a bus, wherein the bus couples to each shift register unit. Each shift register unit comprises a shift register, a first selector circuit, and a second selector circuit. The shift register has an input and an output. The first selector circuit is coupled to the input, while the second selector circuit is coupled to the output. The first selector circuit and the second selector circuit selectively couple to the bus or the next shift register unit.

Abstract: A digital to analog converter of the source driver includes a gamma voltage generator and a data decoder. The gamma voltage generator receives a gamma code to generate an analog gamma voltage. The gamma voltage includes a register, a reference decoder, and a calibrator. The register stores the gamma code. The reference decoder converts the gamma code from the register into the analog gamma voltage. The calibrator, receiving a reference gamma voltage in a calibration mode, includes a comparator and a counter, in which the counter tunes the gamma code according to the control signal generated by the comparator comparing the analog gamma voltage and the reference gamma voltage. The data decoder receives digital pixel data and selects one gamma voltage as a driving voltage based on the digital pixel data.

Abstract: The present invention discloses a signal interface to transmit a data signal to a driving circuit. The signal interface comprises a first circuit, a second circuit and a data bus. The first circuit comprises a first register. The second circuit comprises a selector, a second register, a receiver and a third register. If the data signal is a single-end signal, the first register and the selector receive the data signal. Then, the selector transmits the data signal to the second register. The data bus transmits the signal saved in the first register and the second register to the driving circuit. If the data signal is a serial signal, the selector receives and transmits the data signal to the receiver to have it transferred to a single-end signal. Then, the signal is transmitted to the third register and output via the data bus.

Abstract: A power saving method of a chip-on-glass liquid crystal display. The method first (a) wakes up the source drivers of the LCD and (b) transmitting the image data and control signals from the source driver corresponding to the FPC to the farthest waked source drivers, and then switching them to power-saving mode. Steps (b) and (c) are repeated until all the source drivers are switched to power-saving mode.

Abstract: The present invention discloses a signal interface to transmit a data signal to a driving circuit. The signal interface comprises a first circuit, a second circuit and a data bus. The first circuit comprises a first register. The second circuit comprises a selector, a second register, a receiver and a third register. If the data signal is a single-end signal, the first register and the selector receive the data signal. Then, the selector transmits the data signal to the second register. The data bus transmits the signal saved in the first register and the second register to the driving circuit. If the data signal is a serial signal, the selector receives and transmits the data signal to the receiver to have it transferred to a single-end signal. Then, the signal is transmitted to the third register and output via the data bus.

Abstract: The present invention discloses a shift register circuit comprising a plurality of shift register units and a bus, wherein the bus couples to each shift register unit. Each shift register unit comprises a shift register, a first selector circuit, and a second selector circuit. The shift register has an input and an output. The first selector circuit is coupled to the input, while the second selector circuit is coupled to the output. The first selector circuit and the second selector circuit selectively couple to the bus or the next shift register unit.

Abstract: The present invention discloses a shift register circuit, comprising a plurality of shift register units and a switching circuit. The shift register units are electrically connected in series. The switching circuit electrically connects to the shift register units to divide the shift register units into a first group of shift register units and a second group of shift register units. In the shift register circuit of the present invention, the switching circuit electrically connects the first and the second group of shift register units or electrically disconnects the first group of shift register units from the second group of shift register units according to at least one control signal.

Abstract: A display implemented with a unique circuit arrangement. The display includes a glass substrate, a plurality of serial-connected source drivers and at least one gate driver. The source drivers and the at least one gate driver are disposed on the glass substrate using, for example, chip-on-glass technology. The display further includes at least one flexible connector, such as a flexible printed circuit board. Each of the at least one flexible connector corresponds to a selected one of the source drivers. The selected one of the source drivers is configured to receive image data and control information from the corresponded flexible connector, and convey the image data and the control information to at least one neighboring source driver.

Abstract: A method for transmitting control signals of a liquid crystal display is provided. The LCD includes a timing controller. The method packs the control signals of the timing controller into a control packet which comprises a header field and a control item having a control field and a data field. The header field indicates the start of the control packet, the control field records a type of an event, and the data field records a parameter of the event. The control packet is transmitted on one or a limited number of transmission lines.

Abstract: An identifier for identifying a source driver of a chip-on-glass liquid crystal display and an identifying method thereof are provided. The identifier includes a comparator for receiving a chip identity and a target identity, and generates a triggering signal to activate the source driver if the chip identity coincides with the target identity.

Abstract: A power saving method of a chip-on-glass liquid crystal display. The method first (a) wakes up the source drivers of the LCD and (b) transmitting the image data and control signals from the source driver corresponding to the FPC to the farthest waked source drivers, and then switching them to power-saving mode. Steps (b) and (c) are repeated until all the source drivers are switched to power-saving mode.

Abstract: A liquid crystal display is disclosed, which includes a panel having an array of pixels, a timing controller outputting image data and source control signals, a series of source drivers and a gate driver. One of the source drivers is selected to generate gate control signals by reference to at least one of the source control signals and transmitted to the gate driver. Thus, the gate driver along with the source drivers can drive the panel pixels.

Abstract: A flat type display and method thereof capable of reducing power consumption includes a plurality of shift registers for temporarily storing digital image data, and a plurality of mode-selecting units for determining the shift registers not storing digital data, and then turning off corresponding output operational buffers based on the image resolution. Utilizing such flat type display and method, the power consumption of the flat type display is reduced due to the turning off of selected output operational buffers of the flat type display.