Abstract: An integrated chip including a substrate and a transistor device along the substrate. A plurality of conductive interconnects are over the transistor device. A first under-bump metal (UBM) layer is over the conductive interconnects. A first metal bump is directly over the first UBM layer. A metal-insulator-metal (MIM) capacitor array is over the transistor device and under the first UBM layer. The MIM capacitor array includes a first MIM capacitor and a second MIM capacitor coupled in parallel and disposed directly under the first UBM layer.

Abstract: A high power RF IC capable of impeding parasitic current loss and method of manufacturing the same. First a step of semiconductor front-side processing for the high power RF components that includes inductive components is performed. Afterwards, the backside of semiconductor base is polished to a certain thickness, and then lithography and etching processes is employed for forming a backside trench contact window. A backside deposition for oxide insulation layer can be performed so that the oxide insulation layer can be located in the semiconductor base right under the inductive components for impeding the parasitic current loss generated by the inductive components in the semiconductor base due to electromagnetic induction. Therefore, performance of the inductive components operating in high frequency can be improved.

Abstract: A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be implanted into the semiconductor base under the drain region to form an extended drain heavy-doped region. Then, the patterned resist layer is removed and a heat tempering processing is performed. Finally, a self-aligned salicide is formed on the surfaces of the polysilicon gate and the heavy-ion doped region. The invention utilizes an extended drain heavy-doped region as a resistance ballast between the drain contact and the polysilicon contact surface, which allows high current generated by ESD to be discharged in a more homogeneous way so as to prevent the ESD structure from being damaged.

Abstract: A method of forming poly insulator poly capacitors by using self-aligned salicide process for mixed mode analog devices. These capacitors are formed in the self-aligned salicide process as stacked poly insulator poly (PIP) capacitors. In the self-aligned salicide process, a self-aligned salicide block process is needed to protect the the salicide formation process from electrostatic discharge (ESD) devices such as resistors or capacitors. The oxide layer of the self-aligned salicide block is used as the dielectric layer of the capacitors to form the PIP capacitor. Therefore, some process steps are omitted due to the formation of the PIP capacitors.

Abstract: A semiconductor resistance element and fabrication method thereof. When polysilicon is used as a resistance element, salicides having contacts for connecting external leads are formed on two sides of the polysilicon. If the resistance element has a high resistance coefficient, an interface resistance is produced between the salicide and the block oxide layer. This interface resistance is subject to variations in voltage and temperature, resulting in unstable resistivity. The present invention provides an ion implantation with high concentration for implanting two sides of the polysilicon of the resistance element. This ion implantation with high concentration is performed before the salicides are formed. The polysilicon on two sides of the resistance element under the salicides has a lower resistance coefficient, resulting in reducing the interface resistance between the silicide and the block oxide layer.

Abstract: A high power RF IC capable of impeding parasitic current loss and method of manufacturing the same. First a step of semiconductor front-side processing for the high power RF components that includes inductive components is performed. Afterwards, the backside of semiconductor base is polished to a certain thickness, and then lithography and etching processes is employed for forming a backside trench contact window. A backside deposition for oxide insulation layer can be performed so that the oxide insulation layer can be located in the semiconductor base right under the inductive components for impeding the parasitic current loss generated by the inductive components in the semiconductor base due to electromagnetic induction. Therefore, performance of the inductive components operating in high frequency can be improved.

Abstract: A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric layer, and the upper electrode layer are formed in sequence in a plurality of shallow trench isolation regions to form a trench capacitor. The present invention uses a trench capacitor to substitute for the 3-dimensional structure capacitor to overcome the disadvantages of the conventional capacitor, resulting in increasing the surface area of electrode and the capacitance.

Abstract: A semiconductor resistance element and fabrication method thereof. When polysilicon is used as a resistance element, salicides having contacts for connecting external leads are formed on two sides of the polysilicon. If the resistance element has a high resistance coefficient, an interface resistance is produced between the salicide and the block oxide layer. This interface resistance is subject to variations in voltage and temperature, resulting in unstable resistivity. The present invention provides an ion implantation with high concentration for implanting two sides of the polysilicon of the resistance element. This ion implantation with high concentration is performed before the salicides are formed. The polysilicon on two sides of the resistance element under the salicides has a lower resistance coefficient, resulting in reducing the interface resistance between the suicide and the block oxide layer.

Abstract: A method of forming poly insulator poly capacitors by using self-aligned salicide process for mixed mode analog devices. These capacitors are formed in the self-aligned salicide process by stacked poly insulator poly (PIP). In the self-aligned salicide process, a self-aligned salicide block process is needed for preventing the salicide formation from electrostatic discharge (ESD) devices, resistors, or capacitors. The present invention uses the oxide layer of the self-aligned salicide block for the dielectric layer of the capacitors to form the PIP capacitor. Therefore, some process steps are omitted due to the formation of the PIP capacitors.

Abstract: A processing method for improving a structure of a high voltage device utilizing a gradually reduced concentration between the drain region and the semiconductor substrate so as to reduce the intensity of the electric field to increase the breakdown voltage. A drift region is formed and forms a thin oxide layer and a patterned silicon nitride layer. A first patterned photo resistant is formed on the semiconductor substrate and the patterned silicon nitride layer is etched to define a field oxide region. A thermal process is utilized to form a field oxide layer and the silicon nitride layer and the thin oxide layer are removed. A gate oxide layer and a polysilicon gate structure are formed. A heavily ion dopant area is formed for use as a source/drain. A second patterned photo resistant is formed and used as a mask to form a dopant well area in the drift region.

Abstract: A method for forming a high voltage complementary metal-oxide semiconductor (high voltage CMOS) by utilizing a retrograde ion implantation step. The present invention utilizes a retrograde ion implantation step on a dopant well area, the N-drift region and the N-drift region of the high voltage CMOS structure. After forming the field oxide isolation structure, the present invention utilizes the high voltage ion implantation step to form these dopant areas. The high voltage CMOS structure formed in the present invention is provided with better electronic characteristics. In the present invention, the anti breakdown voltage is higher and the driving current is also larger. The present invention can also shrink the area of the whole devices.

Abstract: A high power RF IC capable of impeding parasitic current loss and method of manufacturing the same. First a step of semiconductor front-side processing for the high power RF components that includes inductive components is performed. Afterwards, the backside of semiconductor base is polished to a certain thickness, and then lithography and etching processes is employed for forming a backside trench contact window. A backside deposition for oxide insulation layer can be performed so that the oxide insulation layer can be located in the semiconductor base right under the inductive components for impeding the parasitic current loss generated by the inductive components in the semiconductor base due to electromagnetic induction. Therefore, performance of the inductive components operating in high frequency can be improved.

Abstract: A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be implanted into the semiconductor base under the drain region to form an extended drain heavy-doped region. Then, the patterned resist layer is removed and a heat tempering processing is performed. Finally, a self-aligned salicide is formed on the surfaces of the polysilicon gate and the heavy-ion doped region. The invention utilizes an extended drain heavy-doped region as a resistance ballast between the drain contact and the polysilicon contact surface, which allows high current generated by ESD to be discharged in a more homogeneous way so as to prevent the ESD structure from being damaged.

Abstract: A processing method of a silicon controlled rectifier (SCR) for ESD protection. In the present invention, a high voltage ion implantation step is utilized to respectively implant the same type ion of comparably high dopant concentration in the first conductive dopant well and in the second conductive dopant well so as to form a first buried dopant area and a second buried dopant area. The silicon controlled rectifier of the present invention can be switch on more quickly and the proper control of the concentration of the buried dopant area is to control the breakdown voltage of the conjunction so as to control of the trigger voltage of the ESD.

Abstract: The present invention provides a manufacturing method of an electrostatic discharge protection device for deep submicron manufacturing processing. In deep submicron manufacturing processing, non-uniform high current causes the electrostatic protection components to be broken while the self-aligned salicide is applied to source/drain region of transistors which include electrostatic discharge (ESD) protection components. For improving the problem, the present invention forms no self-aligned salicide in the electrostatic discharge protection components region but a resistance ballast is formed between the drain contact and the poly gate by utilizing a self-aligned salicide block. It renders the high current generated from electrostatic discharge capable of discharging in a homogeneous manner in order to avoid the electrostatic protection components from being damaged.

Abstract: A PMOS thin film transistor (TFT) with self-align offset region for SRAM application is described. A source and a drain regions are above the gate region. A channel region is formed offset from the gate. An offset region is formed in the channel region having a length of 0.3 to 0.4 .mu.m. The key point of the present invention is the novel offset design of PMOS-TFT as load elements in an SRAM cell. Unlike the conventional offset design which is outside the gate, the offset region of the present invention is a disconnection region inside the gate which can be easily formed by so called self-align technique. Since the gate has a disconnected portion in the offset region, the trench-like profile of the offset region makes the load resistance in the offset region much higher to effectively reduce the leakage current.