Patents by Inventor Jung Gu Lee
Jung Gu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107857Abstract: A display device includes a thin-film transistor, a source/drain electrode and an auxiliary electrode including a first conductive layer and a second conductive layer disposed on the first conductive layer, a via insulating layer having a first opening exposing the auxiliary electrode, a capping layer covering a portion of the auxiliary electrode and a light emitting material layer and a common electrode layer sequentially stacked on the via insulating layer and the capping layer, wherein the source/drain electrode is electrically connected to the thin-film transistor through a contact hole penetrating the interlayer insulating layer, the auxiliary electrode has an undercut, and the capping layer includes a first capping layer covering side surfaces of the first conductive layer of the auxiliary electrode and a second capping layer separated from the first capping layer and disposed on the second conductive layer of the auxiliary electrode.Type: ApplicationFiled: June 20, 2023Publication date: March 28, 2024Applicant: Samsung Display Co., LTD.Inventors: Joon Gu LEE, Hye Jin GWARK, Jae Ik KIM, Hwi KIM, Jung Sun PARK, Yeon Hwa LEE
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Publication number: 20240099114Abstract: A display device may include a first electrode, a second electrode, an emission layer, an intervening layer, and a first encapsulation layer. The second electrode may overlap the first electrode. The emission layer may be disposed between the first electrode and the second electrode, may overlap the first electrode, and may include a light emitting material. The intervening layer may directly contact the second electrode, may be spaced from each of the first electrode and the emission layer, and may include a fluorine compound. A first section of the first encapsulation layer may overlap the emission layer. The intervening layer may be positioned between the second electrode and a second section of the first encapsulation layer.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: Jae Sik KIM, Jae Ik KIM, Jung Sun PARK, Seung Yong SONG, Duck Jung LEE, Yeon Hwa LEE, Joon Gu LEE, Kyu Hwan HWANG
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Publication number: 20240088440Abstract: A lithium secondary battery includes a negative electrode, a positive electrode positioned opposite to the negative electrode, a separator disposed between the negative electrode and the positive electrode, and a non-aqueous electrolyte, wherein the negative electrode includes a silicon-based active material, the silicon-based active material comprises a compound represented by SiOx, wherein 0?x<2, the non-aqueous electrolyte includes a lithium salt, an organic solvent, and an additive, the additive includes a first additive and a second additive, the first additive includes a coumarin-based compound represented by Formula 1, and the second additive includes at least one of lithium fluoromalonato(difluoro)borate (LiFMDFB), lithium difluoro(oxalato)borate (LiDFOB), lithium difluorophosphate (LiDFP), or lithium difluorobis-(oxalate)phosphate (LiDFOP): wherein R and n are described herein.Type: ApplicationFiled: August 17, 2023Publication date: March 14, 2024Applicant: LG Energy Solution, Ltd.Inventors: Yoon Gyo Cho, Chul Haeng Lee, Kyung Mi Lee, Jung Min Lee, Eun Bee Kim, Su Hyeon Ji, Chul Eun Yeom, Jung Gu Han
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Publication number: 20240082208Abstract: A steroid sulfatase inhibitor provided by the present invention is a safe substance without toxicity and adverse effects, has inhibitory activity against various viruses, and thus is capable of effectively preventing, ameliorating, or treating viral infections or diseases caused by viral infections.Type: ApplicationFiled: January 10, 2022Publication date: March 14, 2024Inventors: Jung Taek Seo, Seok Jun Moon, Sung-Jin Kim, Jae Myun Lee, Pil-Gu Park, Su Jin Hwang, Moon Geon Lee
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Publication number: 20180171502Abstract: A method of electroplating on a workpiece having at least one sub-30 nm feature includes applying a first electrolyte chemistry to the workpiece, the chemistry including a metal cation solute species having a concentration in the range of about 50 mM to about 250 mM and a suppressor resulting in polarization greater than 0.75 V and reaching 0.75 V of polarization at a rate greater than 0.25 V/s, and applying an electric waveform, wherein the electric waveform includes a period of ramping up of current followed by a period of partial ramping down of current.Type: ApplicationFiled: December 15, 2016Publication date: June 21, 2018Applicant: APPLIED Materials, Inc.Inventors: Serdar Aksu, Jung Gu Lee, Bart Sakry, Roey Shaviv
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Patent number: 10000860Abstract: A method of electroplating on a workpiece having at least one sub-30 nm feature includes applying a first electrolyte chemistry to the workpiece, the chemistry including a metal cation solute species having a concentration in the range of about 50 mM to about 250 mM and a suppressor resulting in polarization greater than 0.75 V and reaching 0.75 V of polarization at a rate greater than 0.25 V/s, and applying an electric waveform, wherein the electric waveform includes a period of ramping up of current followed by a period of partial ramping down of current.Type: GrantFiled: December 15, 2016Date of Patent: June 19, 2018Assignee: APPLIED Materials, Inc.Inventors: Serdar Aksu, Jung Gu Lee, Bart Sakry, Roey Shaviv
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Patent number: 9143358Abstract: The present invention relates to an electronic document communication system and to an electronic document communication method, which can construct an electronic document communication system for providing not only enterprise/institutions with reliability, but also individuals and small companies.Type: GrantFiled: July 8, 2011Date of Patent: September 22, 2015Assignee: NATIONAL IT INDUSTRY PROMOTION AGENCYInventors: Dae Seob An, Jung Gu Lee, Seong Pil Kong, Yeong Cheol Lim
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Publication number: 20130117400Abstract: The present invention relates to an electronic document distribution system and to an electronic document distribution method, which can construct an electronic document distribution system for providing not only enterprise/institutions with reliability, but also individuals and small companies.Type: ApplicationFiled: July 8, 2011Publication date: May 9, 2013Applicant: NATIONAL IT INDUSTRY PROMOTION AGENCYInventors: Dae Seob An, Jung Gu Lee, Seong Pil Kong, Yeong Cheol Lim
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Publication number: 20130110919Abstract: The present invention relates to creating, distributing, and storing a distribution certificate in an electronic document distribution system which is based on a public electronic address, and particularly to a method for creating/issuing an electronic document distribution certificate, a method for verifying an electronic document distribution certificate, and a system for distributing an electronic document, which makes it possible to provide a transparent and efficient issuing service and to raise the distribution reliability of electronic documents due to the security of the compatibility of the certificate.Type: ApplicationFiled: July 8, 2011Publication date: May 2, 2013Applicant: NATIONAL IT INDUSTRY PROMOTION AGENCYInventors: Dae Seob An, Jung Gu Lee, Seong Pil Kong, Yeong Cheol Lim
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Patent number: 8025983Abstract: A joining method between Fe-based steel and Ti/Ti-based alloys having a joint strength higher than those of base metals by using interlayers. The production of intermetallic compounds at a joint portion between Fe-based steel and Ti/Ti-based alloys can be prevented using interlayers, and strong interface diffusion bonding can be formed at interfaces between interlayers, thereby producing a high-strength joint. Accordingly, the present disclosure can be used to develop high-strength, high-functional advanced composite materials.Type: GrantFiled: July 16, 2009Date of Patent: September 27, 2011Inventors: Min Ku Lee, Jung Gu Lee, Jin-Ju Park, Chang-Kyu Rhee
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Patent number: 7977205Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.Type: GrantFiled: June 14, 2010Date of Patent: July 12, 2011Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Publication number: 20100304549Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.Type: ApplicationFiled: June 14, 2010Publication date: December 2, 2010Applicant: Hynix Semiconductor Inc.Inventors: Cha Deok DONG, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Patent number: 7736991Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.Type: GrantFiled: December 28, 2006Date of Patent: June 15, 2010Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Publication number: 20100124669Abstract: A joining method between Fe-based steel and Ti/Ti-based alloys having a joint strength higher than those of base metals by using interlayers. The production of intermetallic compounds at a joint portion between Fe-based steel and Ti/Ti-based alloys can be prevented using interlayers, and strong interface diffusion bonding can be formed at interfaces between interlayers, thereby producing a high-strength joint. Accordingly, the present disclosure can be used to develop high-strength, high-functional advanced composite materials.Type: ApplicationFiled: July 16, 2009Publication date: May 20, 2010Applicants: Korea Atomic Energy Research Institute, Korea Hydro and Nuclear Power Co., Ltd.Inventors: Min Ku Lee, Jung Gu Lee, Jin-Ju Park, Chang-Kyu Rhee
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Publication number: 20080220605Abstract: The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.Type: ApplicationFiled: December 13, 2007Publication date: September 11, 2008Inventors: Jung Gu Lee, Whee Won Cho, Seong Hwan Myung, Suk Joong Kim
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Publication number: 20080102579Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.Type: ApplicationFiled: December 28, 2006Publication date: May 1, 2008Applicant: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Patent number: 6594236Abstract: An alarm suppressing method for an optical transmission apparatus includes the steps of checking whether a detected alarm is a root alarm, suppressing a first propagation alarm generated by the root alarm when the detected alarm is a root alarm, determining the types of network elements, suppressing a second propagation alarm generated by the root alarm in accordance with the determined types of the network elements, and suppressing a third propagation alarm generated in accordance with the second propagation alarm. The method further includes the steps of recognizing the direction of a detected propagation alarm, retrieving an element next to the recognized direction, checking the kind of the generated propagation alarm, and suppressing a corresponding propagation alarm when a data base includes a root alarm by retrieving from the data base the information relevant to the root alarm in accordance with the kinds of the checked alarms.Type: GrantFiled: December 31, 1998Date of Patent: July 15, 2003Assignee: LG Information & Communications Ltd.Inventor: Jung Gu Lee