Patents by Inventor Jung-Ho Do

Jung-Ho Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218121
    Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Do, Sanghoon Baek
  • Patent number: 12136626
    Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-su Yu, Hyeon-gyu You, Seung-young Lee, Jae-boong Lee
  • Patent number: 12125787
    Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 22, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Boong Lee, Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung, Ji-Su Yu
  • Patent number: 12068325
    Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X?1)-contacted poly pitch (CPP) circuit, which is (X?1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X?1)-CPP circuit, X being an integer greater than 1.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung Ho Do
  • Publication number: 20240274510
    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Inventors: Jung Ho DO, Seungyoung LEE
  • Patent number: 12046635
    Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: July 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Ho Do, Rwik Sengupta
  • Publication number: 20240203974
    Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 20, 2024
    Inventors: JUNG-HO DO, DAL-HEE LEE, JIN-YOUNG LIM, TAE-JOONG SONG, JONG-HOON JUNG
  • Patent number: 12002738
    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: June 4, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Do, Seungyoung Lee
  • Patent number: 11955471
    Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Dal-Hee Lee, Jin-Young Lim, Tae-Joong Song, Jong-Hoon Jung
  • Patent number: 11887914
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: January 30, 2024
    Inventors: Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung
  • Publication number: 20230335492
    Abstract: According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.
    Type: Application
    Filed: January 12, 2023
    Publication date: October 19, 2023
    Inventors: Jung Ho Do, Ji Su Yu, Jae Ha Lee
  • Publication number: 20230307324
    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: JUNG HO DO, Seungyoung Lee
  • Patent number: 11742287
    Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: August 29, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Ho Do
  • Publication number: 20230223319
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Application
    Filed: March 19, 2023
    Publication date: July 13, 2023
    Inventors: JUNG-HO DO, TAE-JOONG SONG, SEUNG-YOUNG LEE, JONG-HOON JUNG
  • Patent number: 11699636
    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: July 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Do, Seungyoung Lee
  • Publication number: 20230207429
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Application
    Filed: March 9, 2023
    Publication date: June 29, 2023
    Inventors: JUNG-HO DO, TAE-JOONG SONG, SEUNG-YOUNG LEE, JONG-HOON JUNG
  • Patent number: 11688737
    Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 27, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Do, Seung Hyun Song
  • Publication number: 20230178558
    Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X?1)-contacted poly pitch (CPP) circuit, which is (X?1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X?1)-CPP circuit, X being an integer greater than 1.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 8, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung Ho DO
  • Patent number: 11626516
    Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Baek, Jeong Soon Kong, Jung Ho Do
  • Patent number: RE49780
    Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 2, 2024
    Inventors: Taejoong Song, Sanghoon Baek, Sungwe Cho, Jung-Ho Do, Giyoung Yang, Jinyoung Lim