Patents by Inventor Jung-Ho Park
Jung-Ho Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250253221Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.Type: ApplicationFiled: April 28, 2025Publication date: August 7, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Gwangjae JEON, Jung-Ho PARK, Seokhyun LEE, Yaejung YOON
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Patent number: 12300589Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.Type: GrantFiled: August 18, 2021Date of Patent: May 13, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Gwangjae Jeon, Jung-Ho Park, Seokhyun Lee, Yaejung Yoon
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Patent number: 12046526Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: GrantFiled: May 3, 2022Date of Patent: July 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
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Publication number: 20240209022Abstract: The present invention relates to novel peptides having anti-inflammatory and tissue regenerative actions and uses thereof.Type: ApplicationFiled: May 4, 2023Publication date: June 27, 2024Applicant: KOREA RESEARCH INSTITUTE OF BIOSCIENCE AND BIOTECHNOLOGYInventors: Chul-Ho LEE, Yong-Hoon KIM, Kyoung-Shim KIM, Jung-Ran NOH, Kyeong-Ryooon LEE, Byoung-Chan KIM, Dong-Hee CHOI, Jae-Hoon KIM, Eun-Jung KANG, Jun GO, Young-Keun CHOI, In-Bok LEE, Yun-Jung SEO, Jung-Hyeon CHOI, Dong-Ho CHANG, Hye-Yeon PARK, Jung-Ho PARK
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Patent number: 12009277Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: GrantFiled: July 18, 2022Date of Patent: June 11, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
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Publication number: 20230420402Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: GWANGJAE JEON, DONGKYU KIM, JUNG-HO PARK, YEONHO JANG
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Patent number: 11791295Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.Type: GrantFiled: February 20, 2020Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gwangjae Jeon, Dongkyu Kim, Jung-Ho Park, Yeonho Jang
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Patent number: 11715645Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: March 28, 2022Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 11668121Abstract: A motor-driven door ratchet includes a catch part configured to lock a vehicle door to a vehicle body by being caught by a striker mounted on the vehicle body. A door locking and release part includes a main motor and is configured to allow the catch part to be locked or released from the striker. An inside emergency operation lever is connected to an inside handle installed in the vehicle door and is configured to be rotated by receiving a manipulation force to allow the vehicle door to be opened by applying torque to the catch part. An outside emergency operation lever is connected to an outside handle installed in the vehicle door and is configured to be rotated by receiving a manipulation force to allow the vehicle door to be opened by applying torque to the catch part.Type: GrantFiled: July 8, 2020Date of Patent: June 6, 2023Assignees: Hyundai Motor Company, Kia Motors Corporation, Pyeong Hwa Automotive Co., Ltd.Inventors: Jinwoo Nam, Kyoung Taek Kwak, Jungho Han, Hyuk Noh, Jung-Ho Park, Ki Ryun Ahn, Jin-Bok Lee, Ji-Woo Joo
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Patent number: 11515260Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.Type: GrantFiled: May 14, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Hye Kim, Dong Kyu Kim, Jung-Ho Park
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Publication number: 20220352050Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
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Publication number: 20220262696Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
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Patent number: 11404346Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: GrantFiled: January 15, 2020Date of Patent: August 2, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
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Publication number: 20220216068Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
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Patent number: 11328970Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: GrantFiled: May 5, 2020Date of Patent: May 10, 2022Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 11322368Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: September 29, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Publication number: 20220077041Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.Type: ApplicationFiled: August 18, 2021Publication date: March 10, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Gwangjae JEON, Jung-Ho PARK, Seokhyun LEE, Yaejung YOON
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Patent number: 11233894Abstract: An electronic device is provided that includes a wireless communication device configured to connect with wireless external devices. The electronic device obtains information regarding the wireless external devices. Before and after a call connection event, it is determined whether each of the wireless external devices includes a microphone based on the information. In response to receiving the call connection event, when it is determined that only one of the wireless external devices includes a microphone, an audio input is obtained from the one of the wireless external devices that includes the microphone. In response to receiving the call connection event, when it is determined that at least two of the wireless external devices each include a respective microphone, an audio input is selectively obtained from a microphone of one of the at least two of the plurality of wireless external devices.Type: GrantFiled: May 18, 2020Date of Patent: January 25, 2022Inventors: Sang-Kyu Park, Seung-Yup Lee, Jung-Ho Park, Soo-Ho Song
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Patent number: 11121064Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.Type: GrantFiled: March 16, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
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Publication number: 20210257223Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: September 29, 2020Publication date: August 19, 2021Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON