Abstract: A semiconductor package includes: a package board; a first semiconductor chip disposed on the package board, and having a first recess portion adjacent to a first front surface of the first semiconductor chip facing the package board; a second semiconductor chip disposed side by side with the first semiconductor chip on the package board, and having a second recess portion adjacent to a second front surface of the second semiconductor chip facing the package board; and an interconnect bridge disposed on the first and second front surfaces, and at least partially disposed in each of the first and second recess portions.

Abstract: A solid oxide cell stack includes a first end plate having a flow path, a solid oxide cell disposed on the first end plate, and a second end plate including a lower region disposed on the solid oxide cell and having a first through-hole, and an upper region disposed on the lower region and having a second through-hole. In the second end plate, an inner sidewall of the upper region forming the second through-hole is inclined such that a width of the second through-hole increases in an upward direction.

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

Abstract: A multilayer capacitor includes: a capacitor body including first and second dielectric layers, internal electrodes, and including first to six surfaces; first and second external electrodes disposed on the third and fourth surfaces, respectively; and third and fourth external electrodes disposed on the fifth and sixth surfaces, respectively. The internal electrodes include: first internal electrode disposed on the first dielectric layer, having both ends connected to the first and second external electrodes, respectively, and having a hole; a second internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode and be connected to the third external electrode; and a third internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode, be spaced apart from the second internal electrode, and be connected to the fourth external electrode.

Abstract: A multilayer capacitor includes: a capacitor body including first and second dielectric layers, internal electrodes, and including first to six surfaces; first and second external electrodes disposed on the third and fourth surfaces, respectively; and third and fourth external electrodes disposed on the fifth and sixth surfaces, respectively. The internal electrodes include: first internal electrode disposed on the first dielectric layer, having both ends connected to the first and second external electrodes, respectively, and having a hole; a second internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode and be connected to the third external electrode; and a third internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode, be spaced apart from the second internal electrode, and be connected to the fourth external electrode.

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

Abstract: A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.

Abstract: An electronic component module includes a semiconductor package having a first surface provided as a mounting surface and a second surface opposing the first surface, and including a semiconductor chip, a component package having a first surface facing the second surface of the semiconductor package, and a second surface opposing the first surface of the component package, the component package including a passive component, and a connector disposed on the second surface of the component package and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface.

Abstract: An electronic component module includes a semiconductor package having a first surface provided as a mounting surface and a second surface opposing the first surface, and including a semiconductor chip, a component package having a first surface facing the second surface of the semiconductor package, and a second surface opposing the first surface of the component package, the component package including a passive component, and a connector disposed on the second surface of the component package and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface.

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

Abstract: An antenna module includes an antenna substrate including a core layer, insulating layers disposed on opposite surfaces of the core layer, and wiring layers including antenna patterns. The antenna substrate has first and second recess portions. The antenna module further includes a passive component disposed in the first recess portion, a semiconductor chip disposed in the second recess portion and having an active surface, an encapsulant encapsulating at least portions of the semiconductor chip and the passive component, and a connection portion disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the semiconductor chip. The passive component has a thickness greater than that of the semiconductor chip, and the first recess portion has a depth greater than that of the second recess portion.

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, having first and second through-holes, spaced apart from each other, and having a wiring structure that connects the first and second surfaces to each other; a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure; a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers; a second passive component disposed in the second through-hole and connected to the redistribution layers; a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component; and a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip.

Abstract: A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.

Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.

Abstract: An antenna module includes an antenna substrate including a core layer, insulating layers disposed on opposite surfaces of the core layer, and wiring layers including antenna patterns. The antenna substrate has first and second recess portions. The antenna module further includes a passive component disposed in the first recess portion, a semiconductor chip disposed in the second recess portion and having an active surface, an encapsulant encapsulating at least portions of the semiconductor chip and the passive component, and a connection portion disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the semiconductor chip. The passive component has a thickness greater than that of the semiconductor chip, and the first recess portion has a depth greater than that of the second recess portion.

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, having first and second through-holes, spaced apart from each other, and having a wiring structure that connects the first and second surfaces to each other; a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure; a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers; a second passive component disposed in the second through-hole and connected to the redistribution layers; a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component; and a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip.

Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.

Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.

Abstract: A semiconductor package includes: an interposer having a first surface and a second surface and including a first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface and disposed on the interposer so that the inactive surface faces the second surface of the interposer; an encapsulant disposed on the second surface of the interposer, including a photosensitive insulating material, and having a first region covering the semiconductor chip and a second region positioned around the semiconductor chip; and a second redistribution layer including second vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer, and second wiring patterns disposed on the encapsulant and having integrated structures with the second vias and the through-vias.