Abstract: A polarizing plate and an optical display apparatus including the same are provided. The polarizing plate includes: a polarizer; and a first retardation layer and a second retardation layer sequentially stacked on a lower surface of the polarizer. The first retardation layer has an in-plane retardation (Re) of 200 nm to 250 nm at a wavelength of 550 nm; the second retardation layer has an in-plane retardation (Re) of 80 nm to 140 nm at a wavelength of 550 nm; and the polarizing plate has a total transmittance difference of 2% or more between total transmittance at a wavelength of 450 nm and total transmittance at a wavelength of 420 nm.

Abstract: An etching composition includes phosphoric acid, a silane compound comprising at least one silicon (Si) atom, and an organic phosphate represented by Formula 1 below: wherein R1 to R3 are independently hydrogen, or a substituted or unsubstituted hydrocarbyl group, and at least one of R1 to R3 is a substituted or unsubstituted hydrocarbyl group.

Abstract: A seatback restraint device for a vehicle allows a seatback to be freely restrained by and released from a striker by rotation and a scissoring operation of first and second latches. The first latch and the second latch are connected to be rotated and operated in a scissoring motion about a main hinge, one side of the first latch and one side of the second latch are connected to each other by a first elastic body, and other sides of the first and second latches are connected to each other by an operating cable, so that the striker inserted into first and second latch recesses is restrained by the scissoring operation of the first and second latches due to elastic force of the first elastic body, and restraint of the striker is released through mutual operation of the first latch or the second latch by pulling the operating cable.

Abstract: A homomorphic operation system according to an embodiment includes a homomorphic encryption device configured to output a first ciphertext data generated based on a first base, a homomorphic encryption server including a storage device storing base conversion table configured to convert ciphertext data based on the first base into a second ciphertext data based on a second base and the first ciphertext data received from the homomorphic encryption device, and a homomorphic encryption operation device configured to perform a predetermined operation using the base conversion table on the first ciphertext data to convert the first ciphertext data into the second ciphertext data based on the second base.

Abstract: A smaller and lighter diffraction light guide plate, and a method of manufacturing the same.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: A polarizing plate and an optical display apparatus are disclosed. A polarizing plate includes a polarizer and a stack of retardation layers on a surface of the polarizer, and the stack of retardation layers includes a second retardation layer and a first retardation layer stacked on the polarizer in sequence from the surface of the polarizer, the second retardation layer being a non-liquid crystal layer, and the stack of retardation layers has an out-of-plane retardation of ?40 nm or more to less than 0 nm at a wavelength of 550 nm and satisfies Relation 1.

Abstract: A storage system includes a memory controller providing a clock signal; a buffer having a first duty cycle corrector to receive the clock signal and a chip selection signal from the memory controller, perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal, a register to store the first data code regarding the chip selection signal, and a sampler to receive a data signal and a data strobe signal regarding the data signal and output a data stream; and a nonvolatile memory having a second duty cycle corrector to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and out a second corrected clock signal, a second data code generation circuit to generate the second data code based on the second corrected clock signal, and a data strobe signal generator to generate the data strobe signal based on the second corrected clock signal an

Abstract: Provided are a polarizing plate and an optical display device comprising same, the polarizing plate comprising a polarizer and a protective layer formed on at least one surface of the polarizer, wherein: the polarizing plate comprises a first area and a second area formed within an image display area; the first area and the second area have different single transmittances in the same wavelength; and the first area has a single transmittance of 45% to 85%, a maximum absorbance of 1.0 to 5.0 in a wavelength in a range from about 270 nm to about 325 nm, a maximum absorbance of 0.5 to 4.0 in a wavelength which exceeds about 325 nm and is lower than or equal to 420 nm, and a maximum absorbance of 0.5 or less in a wavelength in a range from about 500 nm to about 800 nm.

Abstract: A light emitting diode display apparatus includes: a substrate; a driving element region which is formed on the substrate and in which a plurality of driving elements are arranged in a matrix form; and an emitting element region in which a plurality of emitting elements are arranged in a matrix form, wherein the emitting element includes a first electrode which corresponds to each driving element and is electrically connected to each driving element, a second electrode corresponding to the first electrode, and an emitting layer located between the first electrode and the second electrode, wherein an area of the emitting element region is greater than an area of the driving element region.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: The present disclosure provides a method for transfer and assembly of RGB micro-light-emitting diodes using vacuum suction force whereby the vacuum state of micrometer-sized adsorption holes to which micro-light-emitting diodes formed on a mother substrate or a temporary substrate are bonded is controlled selectively, so that only the micro-light-emitting diode devices desired to be detached from the mother substrate or the temporary substrate are detached from the mother substrate or the temporary substrate using vacuum suction force and then transferred to a target substrate.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: The present disclosure provides a method for transfer and assembly of RGB micro-light-emitting diodes using vacuum suction force whereby the vacuum state of micrometer-sized adsorption holes to which micro-light-emitting diodes formed on a mother substrate or a temporary substrate are bonded is controlled selectively, so that only the micro-light-emitting diode devices desired to be detached from the mother substrate or the temporary substrate are detached from the mother substrate or the temporary substrate using vacuum suction force and then transferred to a target substrate

Abstract: The present disclosure provides a method for transferring a semiconductor device using a micro-vacuum module, wherein the micro-vacuum module includes: a vacuum-forming substrate having a plurality of through-holes, which are connected to an external pump module and a vacuum control unit, formed; and a pattern-forming unit equipped with a single channel or a plurality of independent channels, which is coupled to the vacuum-forming substrate, wherein the plurality of channels are formed to be communicated respectively to a plurality of vacuum holes which have a smaller size than the size of a semiconductor device to be transferred, and the plurality of vacuum holes, having a diameter smaller than 100 ?m, are contacted to a micro semiconductor device having a width and a length of 100 ?m or smaller and the micro semiconductor device is transferred using vacuum adsorption.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: Disclosed herein is a display apparatus including a liquid crystal panel configured to display an image; a backlight unit including: a light source; and an optical member disposed at a path of light emitted from the light source toward the liquid crystal panel; a chassis disposed on the backlight unit and having a plurality of insertion holes along edges thereof; and a frame configured to support the liquid crystal panel and the optical member, the liquid crystal panel and the optical member provided between the frame and the chassis, wherein the frame is coupled to the plurality of insertion holes of the chassis by fitting.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.