Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

Abstract: Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

Abstract: Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern extending in a first direction, gate structures spaced apart from each other in the first direction on the active pattern, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner extending along a sidewall of the source/drain contacts. A carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: Semiconductor devices having improved performance and reliability. For example, a semiconductor device may include a substrate, an active pattern extending in a first direction, on the substrate, a plurality of gate structures on the active pattern, each including a gate electrode that crosses the active pattern. A lower active contact may be connected to a source/drain pattern. A trench may expose the lower active contact, and a width of a bottom surface of the trench in the first direction may be greater than a width of an upper surface of the lower active contact in the first direction. An etching stop film may be along the bottom surface of the trench and side walls of the trench, and have an uppermost surface coplanar with an upper surface of an upper active contact that extends through the etching stop film and is connected to the lower active contact.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.

Abstract: A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.

Abstract: A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

Abstract: A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

Abstract: A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

Abstract: A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.

Abstract: A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.

Abstract: Provided is a method of dicing a wafer that is thin and includes a low-K material using plasma without causing chipping and cracking during sawing without using an etch mask and without performing a separate wafer coating process. The method includes recognizing scribe lines of a front side of the wafer by using an image recognizing unit to obtain recognition information, performing two etching processes, wherein at least one includes plasma etching, on a backside of the wafer by using the recognition information to separate the wafer into a plurality of semiconductor chips, and adhering the plurality of semiconductor chips to an extended tape or a die attach film.

Abstract: Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.

Abstract: Provided is a method of dicing a wafer that is thin and includes a low-K material using plasma without causing chipping and cracking during sawing without using an etch mask and without performing a separate wafer coating process. The method includes recognizing scribe lines of a front side of the wafer by using an image recognizing unit to obtain recognition information, performing two etching processes, wherein at least one includes plasma etching, on a backside of the wafer by using the recognition information to separate the wafer into a plurality of semiconductor chips, and adhering the plurality of semiconductor chips to an extended tape or a die attach film.