Abstract: An outpatient prediction method includes obtaining, by an outpatient prediction apparatus, data on a target to be predicted, obtaining, by the outpatient prediction apparatus, past data including at least one of a number of outpatient clinic units in past, a number of outpatients in past, a number of blood-collecting patients in past, a number of computed tomography (CT)/magnetic resonance imaging (MRI) tests in past, a number of outpatients per outpatient clinic unit in past, a number of blood-collecting patients per outpatient number in past, and a number of CT/MRI tests per outpatient number in past, calculating, by the outpatient prediction apparatus, pattern data based on the past data, and predicting, by the outpatient prediction apparatus, at least one of a number of outpatients in future, a number of blood-collecting patients in future, and a number of CT/MRI tests in future based on the pattern data.

Abstract: Provided are a method of predicting waiting days for a medical examination requiring a reservation at a hospital, the method including acquiring examination prescription and execution data, calculating, based on the examination prescription and execution data, an average ratio of executed examinations for each day required from a prescription to the execution thereof, and an average number of prescriptions based on past weekdays, estimating, based on the average number of prescriptions based on past weekdays, an average number of prescriptions based on future weekdays for a predetermined period by using at least one time-series prediction model, calculating a monthly increment in the average number of prescriptions based on future weekdays, compared to the average number of prescriptions based on the past weekdays, and allocating, based on the average number of prescriptions based on the past weekdays and the monthly increment, an expected number of prescriptions based on future weekdays.

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Abstract: A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Abstract: Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern.

Abstract: A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

Abstract: A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Abstract: A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

Abstract: Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern.

Abstract: Disclosed herein are representative embodiments of tools and techniques for using storyboards in controlling a camera for capturing images, photographs, or video. According to one exemplary technique, at least two storyboards are stored. In addition, at least one storyboard identifier from a camera application is received. Also, using the storyboard identifier, a storyboard of the stored at least two storyboards is retrieved. The retrieved storyboard includes a sequence of control frames for controlling a camera. Additionally, a sequence of image frames is captured at least by controlling a camera using the retrieved storyboard.

Abstract: Disclosed herein are representative embodiments of tools and techniques for using storyboards in controlling a camera for capturing images, photographs, or video. According to one exemplary technique, at least two storyboards are stored. In addition, at least one storyboard identifier from a camera application is received. Also, using the storyboard identifier, a storyboard of the stored at least two storyboards is retrieved. The retrieved storyboard includes a sequence of control frames for controlling a camera. Additionally, a sequence of image frames is captured at least by controlling a camera using the retrieved storyboard.

Abstract: Disclosed herein are representative embodiments of tools and techniques for using storyboards in controlling a camera for capturing images, photographs, or video. According to one exemplary technique, at least two storyboards are stored. In addition, at least one storyboard identifier from a camera application is received. Also, using the storyboard identifier, a storyboard of the stored at least two storyboards is retrieved. The retrieved storyboard includes a sequence of control frames for controlling a camera. Additionally, a sequence of image frames is captured at least by controlling a camera using the retrieved storyboard.

Abstract: Disclosed herein are representative embodiments of tools and techniques for using storyboards in controlling a camera for capturing images, photographs, or video. According to one exemplary technique, at least two storyboards are stored. In addition, at least one storyboard identifier from a camera application is received. Also, using the storyboard identifier, a storyboard of the stored at least two storyboards is retrieved. The retrieved storyboard includes a sequence of control frames for controlling a camera. Additionally, a sequence of image frames is captured at least by controlling a camera using the retrieved storyboard.

Abstract: Capturing and storing an optimized images of a subject are described herein. Images of the subject may be captured while in a live mode or burst mode. The photographer or user administering the photographs may wish to have an image with one or more optimized features. Within the plurality of images, the optimized feature for each subject is found and used to compose an optimized image, and the optimized image may be stored.

Abstract: A Doherty power amplifying apparatus includes a harmonic-controlled Doherty amplifier; and an input matching unit and an output matching unit for input matching and output matching the harmonic-controlled Doherty amplifier, respectively. The harmonic-controlled Doherty amplifier includes a carrier amplifier; a peaking amplifier arranged in parallel to the carrier amplifier; and a harmonic control circuit, arranged in front of the output matching unit, for controlling a harmonic component of an output of the Doherty amplifier to enable the Doherty amplifier to perform a switching or saturation operation.

Abstract: A Doherty power amplifying apparatus includes a harmonic-controlled Doherty amplifier; and an input matching unit and an output matching unit for input matching and output matching the harmonic-controlled Doherty amplifier, respectively. The harmonic-controlled Doherty amplifier includes a carrier amplifier; a peaking amplifier arranged in parallel to the carrier amplifier; and a harmonic control circuit, arranged in front of the output matching unit, for controlling a harmonic component of an output of the Doherty amplifier to enable the Doherty amplifier to perform a switching or saturation operation.