Patents by Inventor Jungju Oh

Jungju Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972387
    Abstract: A method for controlling a transport robot is provided. The method includes the steps of: acquiring, when a user makes a request for transport of a target object, information on the user and information on the transport of the target object including a delivery place of the target object; identifying the user on the basis of the information on the user, and determining a place associated with the user as a destination where a transport robot is to transport the target object from the delivery place, with reference to a result of the identification; and causing the target object to be transported to the destination by the transport robot.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 30, 2024
    Assignee: Bear Robotics, Inc.
    Inventors: John Jungwoo Ha, Jungju Oh
  • Patent number: 11885638
    Abstract: According to one aspect of the invention, there is provided a method for generating a map for a robot, the method comprising the steps of: acquiring a raw map associated with a task of the robot; identifying pixels estimated to be a moving obstacle in the raw map, on the basis of at least one of colors of pixels specified in the raw map and sizes of areas associated with the pixels; and performing dilation and erosion operations on the pixels estimated to be the moving obstacle, and determining a polygon-based contour of the moving obstacle.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 30, 2024
    Assignee: Bear Robotics, Inc.
    Inventors: Yeo Jin Jung, Seongjun Park, Jungju Oh
  • Publication number: 20230249356
    Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Applicant: Bear Robotics, Inc.
    Inventors: John Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
  • Patent number: 11660758
    Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: May 30, 2023
    Assignee: Bear Robotics, Inc.
    Inventors: John Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
  • Publication number: 20230011132
    Abstract: A method for controlling a transport robot is provided. The method includes the steps of: acquiring, when a user makes a request for transport of a target object, information on the user and information on the transport of the target object including a delivery place of the target object; identifying the user on the basis of the information on the user, and determining a place associated with the user as a destination where a transport robot is to transport the target object from the delivery place, with reference to a result of the identification; and causing the target object to be transported to the destination by the transport robot.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 12, 2023
    Applicant: Bear Robotics, Inc.
    Inventors: John Jungwoo Ha, Jungju Oh
  • Publication number: 20220206510
    Abstract: According to one aspect of the invention, there is provided a method for generating a map for a robot, the method comprising the steps of: acquiring a raw map associated with a task of the robot; identifying pixels estimated to be a moving obstacle in the raw map, on the basis of at least one of colors of pixels specified in the raw map and sizes of areas associated with the pixels; and performing dilation and erosion operations on the pixels estimated to be the moving obstacle, and determining a polygon-based contour of the moving obstacle.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: Bear Robotics, Inc.
    Inventors: Yeo Jin JUNG, Seongjun PARK, Jungju OH
  • Patent number: 11279042
    Abstract: A robot includes: a base having a plurality of wheels; a motor system mechanically coupled to one or more of the wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion; a support at the top portion, wherein the support is configured to withstand a temperature that is above 135° F.; and a processing unit configured to operate the robot.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 22, 2022
    Assignee: Bear Robotics, Inc.
    Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
  • Publication number: 20200290210
    Abstract: A robot includes: a base having a plurality of wheels; a motor system mechanically coupled to one or more of the wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion; a support at the top portion, wherein the support is configured to withstand a temperature that is above 135° F.; and a processing unit configured to operate the robot.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Applicant: Bear Robotics Korea, Inc.
    Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
  • Publication number: 20200290208
    Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Applicant: Bear Robotics Korea, Inc.
    Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
  • Patent number: 10546157
    Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Jungju Oh, Siddhartha Chhabra, David M. Durham
  • Patent number: 10025956
    Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Abhishek Basak, Siddhartha Chhabra, Jungju Oh, David M. Durham
  • Publication number: 20180107846
    Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 19, 2018
    Applicant: INTEL CORPORATION
    Inventors: JUNGJU OH, SIDDHARTHA CHHABRA, DAVID M. DURHAM
  • Patent number: 9798900
    Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: October 24, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jungju Oh, Siddhartha Chhabra, David M Durham
  • Patent number: 9792229
    Abstract: In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without the encrypted data. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Eugene M. Kishinevsky, Siddhartha Chhabra, Men Long, Jungju Oh, David M. Durham
  • Patent number: 9710675
    Abstract: In an embodiment, a processor includes: at least one core to execute instructions; a cache memory coupled to the at least one core to store data; and a tracker cache memory coupled to the at least one core. The tracker cache memory includes entries to store an integrity value associated with a data block to be written to a memory coupled to the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: David M. Durham, Siddhartha Chhabra, Jungju Oh, Men Long, Eugene M. Kishinevsky
  • Publication number: 20170177505
    Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: ABHISHEK BASAK, SIDDHARTHA CHHABRA, JUNGJU OH, DAVID M. DURHAM
  • Patent number: 9678894
    Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Jungju Oh, Siddhartha Chhabra, David M. Durham
  • Publication number: 20160285892
    Abstract: In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without the encrypted data. Other embodiments are described and claimed.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Eugene M. Kishinevsky, Siddhartha Chhabra, Men Long, Jungju Oh, David M. Durham
  • Publication number: 20160283748
    Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: JUNGJU OH, SIDDHARTHA CHHABRA, DAVID M. DURHAM
  • Publication number: 20160283405
    Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Jungju Oh, Siddhartha Chhabra, David M. Durham