Patents by Inventor Jungju Oh
Jungju Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972387Abstract: A method for controlling a transport robot is provided. The method includes the steps of: acquiring, when a user makes a request for transport of a target object, information on the user and information on the transport of the target object including a delivery place of the target object; identifying the user on the basis of the information on the user, and determining a place associated with the user as a destination where a transport robot is to transport the target object from the delivery place, with reference to a result of the identification; and causing the target object to be transported to the destination by the transport robot.Type: GrantFiled: July 6, 2021Date of Patent: April 30, 2024Assignee: Bear Robotics, Inc.Inventors: John Jungwoo Ha, Jungju Oh
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Patent number: 11885638Abstract: According to one aspect of the invention, there is provided a method for generating a map for a robot, the method comprising the steps of: acquiring a raw map associated with a task of the robot; identifying pixels estimated to be a moving obstacle in the raw map, on the basis of at least one of colors of pixels specified in the raw map and sizes of areas associated with the pixels; and performing dilation and erosion operations on the pixels estimated to be the moving obstacle, and determining a polygon-based contour of the moving obstacle.Type: GrantFiled: December 28, 2020Date of Patent: January 30, 2024Assignee: Bear Robotics, Inc.Inventors: Yeo Jin Jung, Seongjun Park, Jungju Oh
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Publication number: 20230249356Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Applicant: Bear Robotics, Inc.Inventors: John Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
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Patent number: 11660758Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.Type: GrantFiled: March 12, 2019Date of Patent: May 30, 2023Assignee: Bear Robotics, Inc.Inventors: John Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
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Publication number: 20230011132Abstract: A method for controlling a transport robot is provided. The method includes the steps of: acquiring, when a user makes a request for transport of a target object, information on the user and information on the transport of the target object including a delivery place of the target object; identifying the user on the basis of the information on the user, and determining a place associated with the user as a destination where a transport robot is to transport the target object from the delivery place, with reference to a result of the identification; and causing the target object to be transported to the destination by the transport robot.Type: ApplicationFiled: July 6, 2021Publication date: January 12, 2023Applicant: Bear Robotics, Inc.Inventors: John Jungwoo Ha, Jungju Oh
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Publication number: 20220206510Abstract: According to one aspect of the invention, there is provided a method for generating a map for a robot, the method comprising the steps of: acquiring a raw map associated with a task of the robot; identifying pixels estimated to be a moving obstacle in the raw map, on the basis of at least one of colors of pixels specified in the raw map and sizes of areas associated with the pixels; and performing dilation and erosion operations on the pixels estimated to be the moving obstacle, and determining a polygon-based contour of the moving obstacle.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Applicant: Bear Robotics, Inc.Inventors: Yeo Jin JUNG, Seongjun PARK, Jungju OH
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Patent number: 11279042Abstract: A robot includes: a base having a plurality of wheels; a motor system mechanically coupled to one or more of the wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion; a support at the top portion, wherein the support is configured to withstand a temperature that is above 135° F.; and a processing unit configured to operate the robot.Type: GrantFiled: March 12, 2019Date of Patent: March 22, 2022Assignee: Bear Robotics, Inc.Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
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Publication number: 20200290210Abstract: A robot includes: a base having a plurality of wheels; a motor system mechanically coupled to one or more of the wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion; a support at the top portion, wherein the support is configured to withstand a temperature that is above 135° F.; and a processing unit configured to operate the robot.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Applicant: Bear Robotics Korea, Inc.Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
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Publication number: 20200290208Abstract: A robot includes: a base having a plurality of wheels; a body having a bottom portion coupled above the base, and a top portion above the bottom portion, the top portion configured to support food and/or drink; a first camera at the bottom portion, wherein the first camera is oriented to view upward; and a second camera at the top portion, wherein the second camera is configured to view upward.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Applicant: Bear Robotics Korea, Inc.Inventors: Jungwoo Ha, Fangwei Li, Brennand Pierce, Jungju Oh
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Patent number: 10546157Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.Type: GrantFiled: October 24, 2017Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Jungju Oh, Siddhartha Chhabra, David M. Durham
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Patent number: 10025956Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.Type: GrantFiled: December 18, 2015Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Abhishek Basak, Siddhartha Chhabra, Jungju Oh, David M. Durham
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Publication number: 20180107846Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.Type: ApplicationFiled: October 24, 2017Publication date: April 19, 2018Applicant: INTEL CORPORATIONInventors: JUNGJU OH, SIDDHARTHA CHHABRA, DAVID M. DURHAM
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Patent number: 9798900Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.Type: GrantFiled: March 26, 2015Date of Patent: October 24, 2017Assignee: INTEL CORPORATIONInventors: Jungju Oh, Siddhartha Chhabra, David M Durham
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Patent number: 9792229Abstract: In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without the encrypted data. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2015Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Eugene M. Kishinevsky, Siddhartha Chhabra, Men Long, Jungju Oh, David M. Durham
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Patent number: 9710675Abstract: In an embodiment, a processor includes: at least one core to execute instructions; a cache memory coupled to the at least one core to store data; and a tracker cache memory coupled to the at least one core. The tracker cache memory includes entries to store an integrity value associated with a data block to be written to a memory coupled to the processor. Other embodiments are described and claimed.Type: GrantFiled: March 26, 2015Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: David M. Durham, Siddhartha Chhabra, Jungju Oh, Men Long, Eugene M. Kishinevsky
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Publication number: 20170177505Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Applicant: Intel CorporationInventors: ABHISHEK BASAK, SIDDHARTHA CHHABRA, JUNGJU OH, DAVID M. DURHAM
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Patent number: 9678894Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.Type: GrantFiled: March 27, 2015Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Jungju Oh, Siddhartha Chhabra, David M. Durham
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Publication number: 20160285892Abstract: In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without the encrypted data. Other embodiments are described and claimed.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Eugene M. Kishinevsky, Siddhartha Chhabra, Men Long, Jungju Oh, David M. Durham
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Publication number: 20160283748Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Applicant: Intel CorporationInventors: JUNGJU OH, SIDDHARTHA CHHABRA, DAVID M. DURHAM
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Publication number: 20160283405Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Jungju Oh, Siddhartha Chhabra, David M. Durham