Patents by Inventor Jung-Kuk Lee
Jung-Kuk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230390362Abstract: Provided is use of a trigonal agonist having activities to all of glucagon, GLP-1, and GIP receptors, and/or a conjugate thereof in the prevention or treatment of sequelae following respiratory infectious diseases.Type: ApplicationFiled: October 18, 2021Publication date: December 7, 2023Applicant: HANMI PHARM. CO., LTD.Inventors: Jong Suk LEE, Jung Kuk LEE, Seon Myeong LEE, Sang Hyun LEE, Jeong A KIM, Euh Lim OH, Chong Yoon LIM
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Patent number: 11714960Abstract: A syntactic analysis apparatus according to an embodiment of the present disclosure may include an input device receiving a phrase uttered from a user, and a learning device performing at least one or more of extension of an intent output layer for classifying an utterance intent of the user from the uttered phrase and extension of a slot output layer for classifying a slot including information of the phrase and extending a pre-generated utterance syntactic analysis model, such that the uttered phrase is classified into the extended intent output layer and the extended slot output layer, thereby broadly classifying an intent and a slot for the phrase uttered from a user.Type: GrantFiled: June 15, 2020Date of Patent: August 1, 2023Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, HYUNDAI AUTOEVER CORP., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Sung Soo Park, Chang Woo Chun, Chan Ill Park, Su Hyun Park, Jung Kuk Lee, Hyun Tae Kim, Sang goo Lee, Kang Min Yoo, You Hyun Shin, Ji Hun Choi, Sang Hwan Bae
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Publication number: 20210182482Abstract: A syntactic analysis apparatus according to an embodiment of the present disclosure may include an input device receiving a phrase uttered from a user, and a learning device performing at least one or more of extension of an intent output layer for classifying an utterance intent of the user from the uttered phrase and extension of a slot output layer for classifying a slot including information of the phrase and extending a pre-generated utterance syntactic analysis model, such that the uttered phrase is classified into the extended intent output layer and the extended slot output layer, thereby broadly classifying an intent and a slot for the phrase uttered from a user.Type: ApplicationFiled: June 15, 2020Publication date: June 17, 2021Inventors: Sung Soo Park, Chang Woo Chun, Chan Ill Park, Su Hyun Park, Jung Kuk Lee, Hyun Tae Kim, Sang goo Lee, Kang Min Yoo, You Hyun Shin, Ji Hun Choi, Sang Hwan Bae
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Patent number: 9026870Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.Type: GrantFiled: March 13, 2013Date of Patent: May 5, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-kuk Lee, Sang-seok Kang, Woo-seop Kim, Hyun-soo Kim
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Publication number: 20140032984Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.Type: ApplicationFiled: March 13, 2013Publication date: January 30, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-kuk Lee, Sang-seok Kang, Woo-seop Kim, Hyun-soo Kim
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Patent number: 8125236Abstract: A main board according to example embodiments may include a substrate and at least one socket. The at least one socket may directly connect a memory module to the substrate in a direction parallel to the substrate. A memory mounting test system including the main board may occupy a smaller space, because the memory module is connected to the main board in a direction parallel to the main board.Type: GrantFiled: March 29, 2010Date of Patent: February 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Kuk Lee, Seung-Hee Lee
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Patent number: 7979760Abstract: Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.Type: GrantFiled: March 6, 2009Date of Patent: July 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-sul Kim, Seung-hee Lee, Jung-kuk Lee, Hee-joo Choi
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Patent number: 7814379Abstract: A memory module packaging test system may include a plurality of test slots into which a plurality of memory modules may be installed so that the system may simultaneously test the memory modules. The memory module packaging test system may use a server system for a registered dual in-line memory module (RDIMM) or a fully buffered dual in-line memory module (FBDIMM) so that the system may test an unbuffered dual in-line memory module (UDIMM).Type: GrantFiled: June 20, 2007Date of Patent: October 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-kuk Lee, You-keun Han, Hui-chong Shin
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Publication number: 20100257416Abstract: A main board according to example embodiments may include a substrate and at least one socket. The at least one socket may directly connect a memory module to the substrate in a direction parallel to the substrate. A memory mounting test system including the main board may occupy a smaller space, because the memory module is connected to the main board in a direction parallel to the main board.Type: ApplicationFiled: March 29, 2010Publication date: October 7, 2010Inventors: Jung-Kuk Lee, Seung-Hee Lee
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Publication number: 20100169725Abstract: a memory module test system for testing a plurality of memory modules includes a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module. The test system further includes an interface configured to receive a test program for testing the memory module, and a gate array configured to transmit the test program to the buffers using a Joint Test Action Group (JTAG) protocol and to read test results of the test program from the buffers using the JTAG protocol.Type: ApplicationFiled: December 29, 2009Publication date: July 1, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Kuk Lee, Seung Hee Mun, Seung Jin Seo, Woo-Jin Na
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Publication number: 20100043926Abstract: A method for preventing carbon steel from intergranular cracking utilizing a reducing gas instead of nitrogen gas for a heat treatment of feeder pipes for a pressurized heavy water reactor (PHWR) nuclear power plant. This heat treatment protects carbon from oxidation to prevent the formation of decarburized layers so that the feeder pipes can be prevented from intergranular cracking. In addition, intergranular segregation of impurities is inhibited and intergranular strength of the carbon steel is enhanced. Therefore, no intergranular cracking occurs despite the concentration of stress.Type: ApplicationFiled: October 28, 2008Publication date: February 25, 2010Inventors: Nam Hoe HEO, Hong Deok Kim, Ki Tae Kim, Jung Kuk Lee, Yong Chan Jung
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Patent number: 7606110Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.Type: GrantFiled: January 5, 2005Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
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Publication number: 20090228747Abstract: Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.Type: ApplicationFiled: March 6, 2009Publication date: September 10, 2009Inventors: Byoung-sul Kim, Seung-hee Lee, Jung-kuk Lee, Hee-joo Choi
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Patent number: 7487413Abstract: A memory module testing apparatus and method include a test slot adapted to receive a target memory module, wherein the target memory module includes a first memory unit to store information related to the target memory module. The memory module testing apparatus further includes a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit.Type: GrantFiled: April 6, 2006Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-kuk Lee, Seung-jin Seo, You-keun Han, Seung-man Shin, Young-man Ahn
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Publication number: 20080016400Abstract: A memory module packaging test system may include a plurality of test slots into which a plurality of memory modules may be installed so that the system may simultaneously test the memory modules. The memory module packaging test system may use a server system for a registered dual in-line memory module (RDIMM) or a fully buffered dual in-line memory module (FBDIMM) so that the system may test an unbuffered dual in-line memory module (UDIMM).Type: ApplicationFiled: June 20, 2007Publication date: January 17, 2008Inventors: Jung-kuk Lee, You-keun Han, Hui-chong Shin
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Patent number: 7319635Abstract: A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.Type: GrantFiled: October 21, 2005Date of Patent: January 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Man Ahn, Seung-Jin Seo, Seung-Hee Mun, Jong-Cheol Seo, Jung-Kuk Lee, Soon-Deok Jang
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Patent number: 7233157Abstract: A test board for a high-frequency system level test: The test board includes a main board having through holes filled with a conductive material. These holes may be located at a portion of the main board from which an existing module socket has been removed. An interface board has surface mounted device (SMD) pads on front and rear surfaces. The SMD pads on the front surface of the interface board are connected with the SMD pads on the rear surface thereof through cross connection wiring within the interface board for a pin swap. The through holes of the main board are connected with the SMD pads on the rear surface of the interface board via iron cores fixed at a guide. A test module socket is mounted on surfaces of the SMD pads on the front surface of the interface board.Type: GrantFiled: December 28, 2004Date of Patent: June 19, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Kuk Lee, Young-Man Ahn, Seung-Man Shin, Jong-Cheol Seo
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Publication number: 20060280024Abstract: A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.Type: ApplicationFiled: October 21, 2005Publication date: December 14, 2006Inventors: Young-Man Ahn, Seung-Jin Seo, Seung-Hee Mun, Jong-Cheol Seo, Jung-Kuk Lee, Soon-Deok Jang
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Publication number: 20060230249Abstract: A memory module testing apparatus that comprises a test slot adapted to receive a target memory module, wherein the target memory module comprises a first memory unit adapted to store information related to the target memory module, is disclosed. The memory module testing apparatus further comprises a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit. A memory module testing method for the memory module testing apparatus is also disclosed.Type: ApplicationFiled: April 6, 2006Publication date: October 12, 2006Inventors: Jung-kuk Lee, Seung-jin Seo, You-keun Han, Seung-man Shin, Young-man Ahn
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Publication number: 20060044927Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.Type: ApplicationFiled: January 5, 2005Publication date: March 2, 2006Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee