Abstract: The sintered body includes boron carbide, wherein a volume ratio of grains of the boron carbide having a grain size greater than 1 ?m and less than or equal to 4 ?m is 61% to 86% based on a volume ratio of total grains on a surface of the sintered body.

Abstract: The sintered body including silicon oxide and carbon, wherein the sintered body has a D band peak at a wave number of 1,311 cm?1 to 1,371 cm?1 and a G band peak at a wave number of 1,572 cm?1 to 1,632 cm?1 in a Raman spectrum, and wherein the D band peak or the G band peak have a higher intensity than a fifth peak present at a wave number of 1,027 cm?1 to 1,087 cm?1 in the Raman spectrum, is disclosed.

Abstract: The sintered body including boron carbide, wherein the sintered body includes a zone, in which a volume ratio of grains having a grain size of greater than 30 ?m and 60 ?m or less is in a range of 50% to 70% based on a total volume of grains, as observed on a surface of the sintered body, is disclosed.

Abstract: A manufacturing method of a ring-shaped element for an etcher, comprises a granulation operation comprising i) a slurry manufacturing process of preparing a slurry by mixing a raw material including boron carbide, a sinterability enhancer with a solvent; and ii) a granulation process of drying the slurry to prepare granulated raw material; a molding operation of manufacturing a green body by molding the granulated raw material; a sintering operation of carbonizing and sintering the green body to manufacture a sintered body; a shape operation of shaping the sintered body to a ring-shaped element for an etcher. The sinterability enhancer comprises one selected from the group consisting of carbon, boron oxide and combinations thereof.

Abstract: A boron carbide sintered body includes necked boron carbide-containing particles. The thermal conductivity of the boron carbide sintered body at 400° C. is 27 W/m·K or less and the ratio of the thermal conductivity of the boron carbide sintered body at 25° C. to that of the boron carbide sintered body at 800° C. is 1:0.2 to 1:3.

Abstract: A ring-shaped element for an etcher includes a body portion having an outer diameter surface connecting an outer contour of an upper surface and an outer contour of a bottom surface, and an inner diameter surface connected to an inner contour of the upper surface, and a mounting portion having an upper surface connected to the inner diameter surface of the body portion at a position lower than the upper surface of the body portion, and an inner diameter surface connecting an inner contour of the upper surface and an inner contour of a bottom surface. The upper surface of the mounting portion is stepped from the upper surface of the body portion to constitute a substrate mounting portion. The surface or entire body of the ring-shaped element includes necked boron carbide-containing particles, and the thermal conductivity of the ring-shaped element at 400° C. is 27 W/m·K or less.

Abstract: A multi-chip module comprises a first package and at least a second package. The first package includes a substrate, at least a first chip, an encapsulant, and a plurality of solder balls. The substrate has an upper surface, a lower surface, and at least an opening. The first chip is disposed on the upper surface of the substrate and is electrically connected to the substrate. The encapsulant is formed on the upper surface of the substrate to seal the first chip. In addition, the solder balls are placed on the lower surface of the substrate. The second package is embedded in the opening of the substrate of the first package. The second package includes a plurality of electrical terminals which are exposed out of the first package to be similar to the solder balls for external connection. Accordingly, the solder balls and the electrical terminals can be used as SMT connection terminals of the multi-chip module.

Abstract: A multi-chip stack package mainly includes a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate with an active surface facing upwards. The redistribution structure includes a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.

Abstract: A multi-chip stack package mainly comprises a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate by an active surface facing upwards. The redistribution structure comprises a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.

Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

Abstract: A manufacturing method of a ball grid array package mainly comprises providing a carrier unit with an upper surface and a lower surface, mounting a plurality of solder balls on the lower surface of the carrier unit, disposing a protective layer below the lower surface to cover the solder balls, placing a chip on the upper surface of the carrier unit and electrically connecting the carrier and the chip, encapsulating the chip and removing the protective layer so as to form said ball grid array package.

Abstract: A multi-chip module comprises a first package and at least a second package. The first package includes a substrate, at least a first chip, an encapsulant, and a plurality of solder balls. The substrate has an upper surface, a lower surface, and at least an opening. The first chip is disposed on the upper surface of the substrate and is electrically connected to the substrate. The encapsulant is formed on the upper surface of the substrate to seal the first chip. In addition, the solder balls are placed on the lower surface of the substrate. The second package is embedded in the opening of the substrate of the first package. The second package includes a plurality of electrical terminals which are exposed out of the first package to be similar to the solder balls for external connection. Accordingly, the solder balls and the electrical terminals can be used as SMT connection terminals of the multi-chip module.

Abstract: A manufacturing method of a ball grid array package mainly comprises providing a carrier unit with an upper surface and a lower surface, mounting a plurality of solder balls on the lower surface of the carrier unit, disposing a protective layer below the lower surface to cover the solder balls, placing a chip on the upper surface of the carrier unit and electrically connecting the carrier and the chip, encapsulating the chip and removing the protective layer so as to form said ball grid array package.

Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.