Patents by Inventor JUNGMIN JU

JUNGMIN JU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274664
    Abstract: An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.
    Type: Application
    Filed: January 10, 2024
    Publication date: August 15, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jungmin JU, Chansic YOON, Gyuhyun KIL, Junghoon HAN, Weonhong KIM
  • Publication number: 20230276619
    Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.
    Type: Application
    Filed: October 24, 2022
    Publication date: August 31, 2023
    Inventors: Jungmin Ju, Gyuhyun Kil, Hyebin Choi, Doosan Back, Ahrang Choi, Jung-Hoon Han
  • Publication number: 20230095717
    Abstract: Disclosed is a semiconductor device comprising a peripheral word line disposed on a substrate, a lower dielectric pattern covering the peripheral word line and including a first part that covers a lateral surface of the peripheral word line and a second part that covers a top surface of the peripheral word line, a contact plug on one side of the peripheral word line and penetrating the first and second parts, and a filling pattern in contact with the second part of the lower dielectric pattern and penetrating at least a portion of the second part. The contact plug includes a contact pad disposed on a top surface of the lower dielectric pattern, and a through plug penetrating the first and second parts. The filling pattern surrounds a lateral surface of the contact pad. The first and second parts include the same material.
    Type: Application
    Filed: July 12, 2022
    Publication date: March 30, 2023
    Inventors: JUNGMIN JU, CHAN-SIC YOON, GYUHYUN KIL, Doosan BACK, JUNG-HOON HAN