Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.

Abstract: An intra prediction method and a device using the intra prediction method are provided. The intra prediction method includes the steps of: deriving a current prediction mode as a prediction mode of a current block; constructing neighboring samples of the current block with available reference samples; filtering the available reference samples; and generating predicted samples of the current block on the basis of the filtered available reference samples. The filtering step includes performing the filtering using the available reference sample located in the prediction direction of the current prediction mode and a predetermined number of available reference samples neighboring to the prediction direction of the current prediction mode.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method according to the present disclosure is performed by an image decoding apparatus. The image decoding method may comprise deriving a prediction sample of a current block based on motion information of the current block, determining whether prediction refinement with optical flow (PROF) applies to the current block, deriving, based on that the PROF applies to the current block, a difference motion vector for each sample position in the current block, deriving a gradient for each sample position in the current block, deriving a PROF offset based on the difference motion vector and the gradient, and deriving a refined prediction sample for the current block based on the PROF offset.

Abstract: The present invention includes obtaining block type identification information on a partition of the current macroblock when the current macroblock is intra-mixed specifying a bock type of the current macroblock based on the block type identification information, obtaining an intra prediction mode of the current macroblock according to the block type of the partition of the current macroblock, and predicting the current macroblock using the intra prediction mode and a pixel value of a neighboring block.

Abstract: A display driver includes first and second level shifters, respectively receiving a digital signal's most significant bit (MSB) and the digital signal's non-MSB. The first level shifter includes a first input terminal, a first output terminal via which a signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a signal input to the second input terminal is output. The second level shifter includes a third input terminal, a third output terminal via which a signal input to the third input terminal is output, a fourth input terminal, and a fourth output terminal via which a signal input to the fourth input terminal is output. The first input terminal receives an inverted MSB, the second input terminal receives the MSB, the third input terminal receives the non-MSB, and the fourth input terminal receives the inverted non-MSB.

Abstract: A method of generating a defect image for deep learning and a system therefor are provided. The method and the system are intended to be used in generating training data for an artificial intelligence algorithm. More specifically, the training data are defect images required to train an algorithm that identifies a defect from a product.

Abstract: A display driver includes first and second level shifters, respectively receiving a digital signal's most significant bit (MSB) and the digital signal's non-MSB. The first level shifter includes a first input terminal, a first output terminal via which a signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a signal input to the second input terminal is output. The second level shifter includes a third input terminal, a third output terminal via which a signal input to the third input terminal is output, a fourth input terminal, and a fourth output terminal via which a signal input to the fourth input terminal is output. The first input terminal receives an inverted MSB, the second input terminal receives the MSB, the third input terminal receives the non-MSB, and the fourth input terminal receives the inverted non-MSB.

Abstract: A pixel includes an organic light emitting diode (OLED); a first transistor between a driving power and a first node, having a gate connected to a control line; a second transistor between the first node and a second node, having a gate connected to a second electrode of a seventh transistor; a third transistor between the second node and an anode electrode of the OLED, having a gate connected to the control line; a fourth transistor between the first node and a data line; a fifth transistor between the second node and a storage capacitor; a sixth transistor between an initialization power and the anode electrode, the fourth to sixth transistors having gates connected to a scan line; the seventh transistor connected to the initialization power and the gate of the second transistor, having a gate connected to another scan line, all transistors being oxide semiconductor thin film transistors.

Abstract: A pixel includes an organic light emitting diode (OLED), a first transistor connected to a driver and a first node, having a gate connected to a control line, a second transistor between to the first node and a second node, having a gate connected to a third node, a third transistor connected to an anode of the OLED, having a gate connected to the control line, a fourth transistor between the first node and a data line, having a gate connected to a scan line, a fifth transistor between the second and third nodes, having a gate connected to the scan line, a sixth transistor between an initializing line and the anode, having a gate connected to the scan line, a seventh transistor between the initializing line and the third node, having a gate connected to another scan line, and a storage capacitor between the driver and the third node.

Abstract: A display driving circuit is provided. The display driving circuit includes: an input control circuit configured to output an input current in response to a sensing current output from at least one pixel; a sampling circuit configured to output a sampling voltage which is a reference voltage during a reset period, and which is a voltage varying based on the reference voltage and the input current during a signal period; and an accumulating circuit configured to generate an output voltage by accumulating variation values of the sampling voltage, and provide the generated output voltage to an analog-to-digital converter (ADC) circuit, wherein the sampling voltage decreases or increases from the reference voltage according to the input current during the signal period.

Abstract: A pixel includes an organic light emitting diode (OLED), a first transistor connected to a driver and a first node, having a gate connected to a control line, a second transistor between to the first node and a second node, having a gate connected to a third node, a third transistor connected to an anode of the OLED, having a gate connected to the control line, a fourth transistor between the first node and a data line, having a gate connected to a scan line, a fifth transistor between the second and third nodes, having a gate connected to the scan line, a sixth transistor between an initializing line and the anode, having a gate connected to the scan line, a seventh transistor between the initializing line and the third node, having a gate connected to another scan line, and a storage capacitor between the driver and the third node.

Abstract: A pixel includes an organic light emitting diode (OLED); a first transistor between a driving power and a first node, having a gate connected to a control line; a second transistor between the first node and a second node, having a gate connected to a second electrode of a seventh transistor; a third transistor between the second node and an anode electrode of the OLED, having a gate connected to the control line; a fourth transistor between the first node and a data line; a fifth transistor between the second node and a storage capacitor; a sixth transistor between an initialization power and the anode electrode, the fourth to sixth transistors having gates connected to a scan line; the seventh transistor connected to the initialization power and the gate of the second transistor, having a gate connected to another scan line, all transistors being oxide semiconductor thin film transistors.

Abstract: Disclosed is an energy harvesting apparatus. The energy harvesting apparatus includes a rectifier for rectifying an alternating current (AC) voltage supplied from an energy source into a direct current (DC) voltage, a charging unit for storing an output voltage of the rectifier, and a maximum power point tracker selectively connected between the rectifier and the charging unit, for differentiating the output voltage of the rectifier in a first connection state, and for controlling the output voltage of the rectifier based on a differentiation result.

Abstract: Provided is a ramp signal generating apparatus. The ramp signal generating apparatus includes N (N is a natural number) ramp signal generating cells that are connected in series to each other. Each of the ramp signal generating cells includes a power voltage unit for supplying current source, a latch unit for latching an output voltage of the power voltage unit, and a switch unit for outputting the voltage latched by the latch unit as an output voltage in response to an input signal.

Abstract: Disclosed is an energy harvesting apparatus. The energy harvesting apparatus includes a rectifier for rectifying an alternating current (AC) voltage supplied from an energy source into a direct current (DC) voltage, a charging unit for storing an output voltage of the rectifier, and a maximum power point tracker selectively connected between the rectifier and the charging unit, for differentiating the output voltage of the rectifier in a first connection state, and for controlling the output voltage of the rectifier based on a differentiation result.

Abstract: Provided is a ramp signal generating apparatus. The ramp signal generating apparatus includes N (N is a natural number) ramp signal generating cells that are connected in series to each other. Each of the ramp signal generating cells includes a power voltage unit for supplying current source, a latch unit for latching an output voltage of the power voltage unit, and a switch unit for outputting the voltage latched by the latch unit as an output voltage in response to an input signal.

Abstract: Provided is a single inductor multiple output (SIMO) direct current-to-direct current (DC/DC) converter that may perform DC/DC conversion by transferring, to output nodes, input current that is input and thereby stored in a single inductor. An output selection unit of the SIMO DC/DC converter may select, from output nodes, a first output node to be supplied with current from a driving unit, and provide output voltage of the first output node and reference voltage of the first output node to a hysteresis comparison unit. The hysteresis comparison unit may control on-time and/or inductor peak current by determining whether the output voltage of the first output node is higher than the reference voltage of the first output node by at least a first threshold, and whether the output voltage of the first output voltage is lower than the reference voltage of the first output voltage by at least a second threshold.

Abstract: Provided is a single inductor multiple output (SIMO) direct current-to-direct current (DC/DC) converter that may perform DC/DC conversion by transferring, to output nodes, input current that is input and thereby stored in a single inductor. An output selection unit of the SIMO DC/DC converter may select, from output nodes, a first output node to be supplied with current from a driving unit, and provide output voltage of the first output node and reference voltage of the first output node to a hysteresis comparison unit. The hysteresis comparison unit may control on-time and/or inductor peak current by determining whether the output voltage of the first output node is higher than the reference voltage of the first output node by at least a first threshold, and whether the output voltage of the first output voltage is lower than the reference voltage of the first output voltage by at least a second threshold.

Abstract: Non-activated tissue-regeneration polypeptides (TRPs) and their preparation methods are disclosed. The TRPs include: a protein transduction domain (PTD) making the polypeptides to permeate a cell membrane without cell membrane receptors; a furin activation domain (FAD) which has at least one proprotein convertase cleavage site and which can be cleaved by the proprotein convertase and activate a tissue regeneration domain (TRD) in cells; and a tissue regeneration domain (TRD) which can be activated by the proprotein convertase cleavage of the FAD to stimulate the growth or formation of tissues or to induce the regeneration of tissues. The TRPs can be mass-produced by cultured bacteria, such as recombinant E. coli, are in a non-activated state before in vivo administration, and their separation, purification, handling, storage and administration are simple and convenient.

Abstract: The present invention relates to non-activated Wnt inhibition polypeptides (WIPs) containing: (a) a protein transduction domain (PTD) which enables said WIPs to permeate a cell membrane without the aid of a cell membrane receptor; and (b) a Wnt antagonist domain which is inactive by itself, but is activated in mammalian cells and then secreted out of the cells to function to inhibit Wnt signal transduction. Also, the invention relates to a method for preparing said non-activated WIPs, and a pharmaceutical composition containing said WIPs as active ingredients. Said non-activated WIPs can be produced in large quantities through the culture of bacteria such as E coli., and are biochemically inactive before being administered into the human body, and thus the production cost thereof is only one several tenths of that of previously known active proteins (sFRPs, DKKs, etc.