Abstract: Plural first charge accumulation layers are arranged on a first gate-insulating film, and divided in the first direction and the second direction. Plural second charge accumulation layers are arranged on a second gate-insulating film and divided in the first direction and the second direction. An intermediate insulating film is arranged on the side surface of the first charge accumulation layers and on the side surface of the second charge accumulation layers. The control electrode includes a side-surface portion, which is arranged on the side surface of the intermediate insulating film, extends in the second direction, and faces via the intermediate insulating film to the side surface of the first charge accumulation layer and the side surface of the second charge accumulation layer, and a pad portion arranged monolithically on the lower portion of the side-surface portion and having a width larger than the film thickness of the side-surface portion.

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract: A semiconductor device including a semiconductor substrate; a memory cell region formed in the semiconductor substrate and including a plurality of memory cells; a peripheral circuit region formed in the semiconductor substrate; a first element isolation trench with a first width formed in the memory cell region; a second element isolation trench with a second width greater than the first width formed in the peripheral circuit region; a first oxide film formed along an inner surface of the first element isolation trench; a first coating oxide film formed along the first oxide film and filling the first element isolation trench; a second oxide film formed along a sidewall of the second element isolation trench; a third oxide film formed above a bottom of the second element isolation trench; and a second coating oxide film formed above the third oxide film and filling the second element isolation trench.

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section be

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section be

Abstract: A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes has a stacked gate structure which has a first insulating film, charge storage layer, second insulating film and control gate stacked on a semiconductor substrate. The uppermost surface of the oxide film is set higher than the uppermost surface of the control gate.