Abstract: A method of operating a data storage device includes generating at least one pseudo noise (PN) sequence using logical information and physical information for the data storage device. The method also includes converting first data into second data using the at least one PN sequence. The logical information may be a logical address for the data storage device, and the physical information may be a physical address for the data storage device.

Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract: A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.

Abstract: A nonvolatile memory device includes a data generating unit for generating a first reference value randomly or pseudo-randomly according to a first program request to program data in a memory cell, a seed selecting unit for selecting at least one of a plurality of seeds using the first reference value, and a randomizer for generating randomized data by using the selected seed. The data generating unit regenerates the first reference value as a second reference value different from the first reference value when a second program request is made, and the seed selecting unit selects another seed using the second reference value.

Abstract: A method of operating a memory system including a first function block and a second function block includes generating a first authentication response indicating physical characteristics of the memory system, via the second function block, in response to a first authentication request received from the first function block; performing an error correction decoding on the first authentication response, via the first function block, by using first parity data corresponding to the first authentication request; and determining whether the second function block is authentic, depending on a result of the error correction decoding.

Abstract: A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

Abstract: A method of operating a data storage device according to an exemplary embodiment of the present inventive concepts includes generating at least one pseudo noise (PN) sequence using logical information and physical information for the data storage device, and converting first data into second data using the at least one PN sequence. Generating the at least one PN sequence includes generating a random seed based on the logical information and the physical information, and generating the at least one PN sequence using the random seed. The logical information may be a logical page address for the data storage device, and the physical information may be a physical page address for the data storage device.

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information, regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells, in a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract: A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.

Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract: A data processing which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

Abstract: A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data.

Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

Abstract: A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period.

Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.