Patents by Inventor Jungsu Kang

Jungsu Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230059079
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.
    Type: Application
    Filed: June 11, 2021
    Publication date: February 23, 2023
    Inventors: Jun XIA, Tao LIU, Qiang WAN, Jungsu KANG, Kangshu ZHAN, Sen LI
  • Publication number: 20220285162
    Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.
    Type: Application
    Filed: December 7, 2021
    Publication date: September 8, 2022
    Inventors: JUNGSU KANG, Sen Li, Qiang Wan, Tao Liu
  • Patent number: 11348820
    Abstract: The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 31, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jiangyi Jin, Jungsu Kang
  • Publication number: 20220139753
    Abstract: The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: Jiangyi JIN, Jungsu KANG
  • Publication number: 20210376059
    Abstract: The method for preparing the hole in the semiconductor device includes: providing a base to be etched and forming a mask layer on the base to be etched; forming a first pattern layer arranged in an array on the mask layer; etching the mask layer by using the first pattern layer as a mask to form a first hole and a second pattern layer; depositing a protective layer on a side of the second pattern layer away from the base to be etched, the protective layer simultaneously covering a side wall and a bottom portion of the first hole; etching the protective layer which covers the bottom portion of the first hole; and etching a supporting layer by using the second pattern layer and the protective layer which covers the side wall of the first hole as a mask to form a second hole.
    Type: Application
    Filed: August 13, 2021
    Publication date: December 2, 2021
    Inventors: Jun XIA, Tao Liu, Qiang Wan, Jungsu Kang, Kangshu Zhan, Sen Li