Patents by Inventor Jung Tae Sung
Jung Tae Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369212Abstract: A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input/output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.Type: ApplicationFiled: March 6, 2023Publication date: November 16, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Tae SUNG, Yun Sun Jang, Moo Rym Choi
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Publication number: 20230371255Abstract: Provided are a memory device, a method of fabricating the same, and an electronic system including the same. The memory device includes a peripheral circuit structure and a cell structure on the peripheral circuit structure. The cell structure comprises a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and having a first conductivity type, gate electrodes on the first surface of the cell substrate, a channel structure intersecting the gate electrodes and connected to the cell substrate, a first impurity region that is in the cell substrate adjacent to the second surface and has a second conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate.Type: ApplicationFiled: January 10, 2023Publication date: November 16, 2023Inventors: MOO RYM CHOI, Jung Tae Sung, Yun Sun Jang
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Patent number: 11723200Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.Type: GrantFiled: August 11, 2021Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kang Min Kim, Jin Hyuk Kim, Jung Tae Sung, Joong Shik Shin, Sung Hyung Lee
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Publication number: 20210375906Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.Type: ApplicationFiled: August 11, 2021Publication date: December 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kang Min KIM, Jin Hyuk KIM, Jung Tae SUNG, Joong Shik SHIN, Sung Hyung LEE
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Patent number: 11121148Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.Type: GrantFiled: June 26, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kang Min Kim, Jin Hyuk Kim, Jung Tae Sung, Joong Shik Shin, Sung Hyung Lee
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Publication number: 20210202516Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.Type: ApplicationFiled: June 26, 2020Publication date: July 1, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kang Min KIM, Jin Hyuk KIM, Jung Tae SUNG, Joong Shik SHIN, Sung Hyung LEE
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Patent number: 10916563Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.Type: GrantFiled: June 26, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin
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Publication number: 20200203366Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.Type: ApplicationFiled: June 26, 2019Publication date: June 25, 2020Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin