Abstract: A method and module for programmable power management and a system on chip are disclosed. The module includes: a token ring and an operation unit. The token ring is provided with a cyclically running token and forming a clock information. The operation unit is configured to perform a corresponding power management operation according to a predetermined operation step register and the token; wherein the step register records a time sequence for performing power management operations, the time sequence being represented by the clock information.

Abstract: A method and module for programmable power management and a system on chip are disclosed. The module includes: a token ring and an operation unit. The token ring is provided with a cyclically running token and forming a clock information. The operation unit is configured to perform a corresponding power management operation according to a predetermined operation step register and the token; wherein the step register records a time sequence for performing power management operations, the time sequence being represented by the clock information.

Abstract: A memory controller, a method of controlling the same, and a semiconductor memory device having the same are provided. The memory controller includes a cache memory provided between an external host and a nonvolatile memory; and a memory manager suitable for storing a plurality of determination values respectively corresponding to a plurality of addresses of the cache memory, wherein the memory manager selects one of the plurality of addresses as a load address corresponding to data to be loaded in the cache memory based on the plurality of the determination values, and initialize the determination value corresponding to the load address based on a type of a command from the host.

Abstract: A semiconductor device includes first power lines through which first power is supplied, a plurality of unit regions defined by the first power lines, and second power lines through which second power is supplied. Each of the unit regions includes a logic circuit suitable for operating by receiving the first power from at least one of the first power lines during a normal mode, and a retention circuit suitable for operating by receiving the second power from at least one of the second power lines, receiving data from the logic circuit when an operation mode changes from the normal mode to a sleep mode, and keeping the data during the sleep mode. The logic circuit is electrically separated from the second power lines.