Abstract: A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.

Abstract: A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.

Abstract: A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.

Abstract: A light emitting display device includes a pixel circuit including: a first transistor having a first electrode connected to a first node coupled to a first power supply line, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor having a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to a first gate line; a light emitting diode connected to the first transistor; a first capacitor having a first electrode connected to the third node and a second electrode connected to a conductive line and an anode electrode of the light emitting diode; and a second capacitor having a first electrode connected to the third node and a second electrode connected to a constant voltage source which supplies a DC voltage.

Abstract: The present disclosure describes an organic light emitting display device including: a display panel including data lines, gate lines, emission lines, and pixels, a data driver applying data signals to the data lines, and a gate driver applying gate signals and emission signals to the gate lines and the emission lines, respectively. At least one of the pixels may be operated in a first period in which a data voltage is applied, a second period in which the data voltage is remained and a driving current is provided according to the data voltage, and a third period in which the data voltage is remained and light emitting is not performed, where a ratio between lengths of the second and third periods can be adjusted. The at least one pixel may receive a preset voltage in the second period and the third period.

Abstract: A light emitting display device includes a pixel circuit including: a first transistor having a first electrode connected to a first node coupled to a first power supply line, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor having a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to a first gate line; a light emitting diode connected to the first transistor; a first capacitor having a first electrode connected to the third node and a second electrode connected to a conductive line and an anode electrode of the light emitting diode; and a second capacitor having a first electrode connected to the third node and a second electrode connected to a constant voltage source which supplies a DC voltage.

Abstract: The present disclosure describes an organic light emitting display device including: a display panel including data lines, gate lines, emission lines, and pixels, a data driver applying data signals to the data lines, and a gate driver applying gate signals and emission signals to the gate lines and the emission lines, respectively. At least one of the pixels may be operated in a first period in which a data voltage is applied, a second period in which the data voltage is remained and a driving current is provided according to the data voltage, and a third period in which the data voltage is remained and light emitting is not performed, where a ratio between lengths of the second and third periods can be adjusted. The at least one pixel may receive a preset voltage in the second period and the third period.

Abstract: Disclosed herein is a gate driver including a plurality of stages. The nth stage of the plurality of stages includes a first scan signal output unit configured to output the kth clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state, and an emission control signal output unit configured to output a gate high voltage through an emission control signal output node when a voltage of the first scan signal output node and a voltage of an EQ-node are at the high state by an emission control clock. The emission control signal output unit is electrically connected to the Q-node. The gate driver includes a scan signal output and an emission control signal output, so that GIPs having the same configuration can be disposed on the left and right sides of a display panel.

Abstract: The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and a first scan signal output from the scan signal generation circuit.

Abstract: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node.

Abstract: The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit.

Abstract: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node.

Abstract: Disclosed herein is a gate driver. The gate driver included a plurality of stages. The nth stage of the plurality of stages includes a first scan signal output unit configured to output the kth clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state, and an emission control signal output unit configured to output a gate high voltage (VGH) through an emission control signal output node when a voltage of the first scan signal output node is at the high state and a voltage of an EQ-node is at the high state by an emission control clock (where n and k are positive integers). The emission control signal output unit is electrically connected to the Q-node. The gate driver includes a scan signal output part as well as an emission control signal output part, so that GIPs having the same configuration can be disposed on the left and right sides of a display panel.

Abstract: The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and a first scan signal output from the scan signal generation circuit.

Abstract: The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit.