Patents by Inventor Jun Ho Cha

Jun Ho Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011536
    Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Il Lee, Ji-Mo Gu, Hyun-Mog Park, Tak Lee, Jun-Ho Cha, Sang-Jun Hong
  • Patent number: 11004866
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung il Lee, Jun Ho Cha
  • Patent number: 10825832
    Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Mo Gu, Kyeong Jin Park, Hyun Mog Park, Byoung Il Lee, Tak Lee, Jun Ho Cha
  • Publication number: 20200185412
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: TAK LEE, SU BIN KANG, JI MO GU, YU JIN SEO, BYOUNG iL LEE, JUN HO CHA
  • Publication number: 20200176470
    Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Inventors: Ji Mo GU, Kyeong Jin PARK, Hyun Mog PARK, Byoung II LEE, Tak LEE, Jun Ho CHA
  • Patent number: 10672781
    Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Ji Mo Gu, Tak Lee, Jun Ho Cha
  • Publication number: 20200144277
    Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each
    Type: Application
    Filed: December 23, 2019
    Publication date: May 7, 2020
    Inventors: Byoung Il LEE, Ji Mo GU, Tak LEE, Jun Ho CHA
  • Patent number: 10566346
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Patent number: 10553605
    Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Mo Gu, Kyeong Jin Park, Hyun Mog Park, Byoung Il Lee, Tak Lee, Jun Ho Cha
  • Patent number: 10515819
    Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hoon Park, Joong Shik Shin, Byoung Il Lee, Jong Ho Woo, Eun Taek Jung, Jun Ho Cha
  • Patent number: 10515974
    Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Ji Mo Gu, Tak Lee, Jun Ho Cha
  • Publication number: 20190244969
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: August 22, 2018
    Publication date: August 8, 2019
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Publication number: 20190035805
    Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 31, 2019
    Inventors: Byoung-Il Lee, Ji-Mo Gu, Hyun-Mog Park, Tak Lee, Jun-Ho Cha, Sang-Jun Hong
  • Publication number: 20190019807
    Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 17, 2019
    Inventors: JI MO GU, Kyeong Jin Park, Hyun Mog Park, Byoung ll Lee, Tak Lee, Jun Ho Cha
  • Publication number: 20190013206
    Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.
    Type: Application
    Filed: December 18, 2017
    Publication date: January 10, 2019
    Inventors: Ji Hoon PARK, Joong Shik SHIN, BYOUNG IL LEE, Jong Ho WOO, Eun Taek JUNG, Jun Ho CHA
  • Publication number: 20180374862
    Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each
    Type: Application
    Filed: March 19, 2018
    Publication date: December 27, 2018
    Inventors: Byoung Il LEE, Ji Mo GU, Tak LEE, Jun Ho CHA
  • Patent number: 9052295
    Abstract: Provided are a panel inspection method and apparatus, the panel inspection method including: (a) determining if a variance value of luminance of a captured image of a panel is greater than a reference value, and searching for an original image and at least one secondary reflective image of a defect of the panel if it is determined that the variance value is greater than the reference value; and (b) determining whether the defect is an actual defect or an impurity disposed on the panel based on at least one of a difference in a luminance characteristic between the original image and the secondary reflective image and a number of the searched secondary reflective image.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG TECHWIN CO., LTD.
    Inventors: Je-Youl Chon, Jun-Ho Cha, Jae-Ho Jeong, Yun-Won Park
  • Publication number: 20140307944
    Abstract: Provided are a panel inspection method and apparatus, the panel inspection method including: (a) determining if a variance value of luminance of a captured image of a panel is greater than a reference value, and searching for an original image and at least one secondary reflective image of a defect of the panel if it is determined that the variance value is greater than the reference value; and (b) determining whether the defect is an actual defect or an impurity disposed on the panel based on at least one of a difference in a luminance characteristic between the original image and the secondary reflective image and a number of the searched secondary reflective image.
    Type: Application
    Filed: August 22, 2013
    Publication date: October 16, 2014
    Inventors: Je-Youl CHON, Jun-Ho CHA, Jae-Ho JEONG, Yun-Won PARK
  • Patent number: 8816838
    Abstract: A transmission position indicator for a vehicle may include a housing, a PCB (printed circuit board) embedded in the housing, wherein a light source may be provided at a predetermined position on the PCB, a light guide plate provided above the PCB and receiving light from the light source, wherein the light guide plate includes light-diffusion-ink patterns printed on a surface thereof, each of the light-diffusion-ink patterns having ink dots, and a cover coupled to an upper end of the housing, wherein the cover may be made of opaque material and includes gear indication characters therein, the gear indication characters being made of transparent material, so that the light transmitted from the light guide plate may be emitted outside the cover through the gear indication characters.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: August 26, 2014
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Jung Hoon Woo, Jun Ho Cha, Yang Gi Lee
  • Patent number: 8672524
    Abstract: A rear lamp apparatus for a vehicle may include a plurality of reflectors mounted in a rear lamp housing of the vehicle to reflect light emitted from light sources at various angles and a light guide provided inside the reflectors and having end portions on which the light sources are mounted to guide the light emitted from the light sources through the light guide.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 18, 2014
    Assignee: Hyundai Motor Company
    Inventors: Jun Ho Cha, Byeong Ho Jeong, Yang Gi Lee