Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: An apparatus, method, chipset, and non-transitory computer-readable storage medium for controlling power are provided. The apparatus includes a receiver configured to receive a data frame and first information related to a next data frame of the data frame; and a controller configured to determine an operation mode as an active mode or a sleep mode based on destination address information of the next data frame and duration information indicating a time during which transmission of the next data frame occurs, wherein the destination address information and the duration information are included in the first information.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: An apparatus, method, chipset, and non-transitory computer-readable storage medium for controlling power are provided. The apparatus includes a receiver configured to receive a data frame and first information related to a next data frame of the data frame; and a controller configured to determine an operation mode as an active mode or a sleep mode based on destination address information of the next data frame and duration information indicating a time during which transmission of the next data frame occurs, wherein the destination address information and the duration information are included in the first information.

Abstract: Methods and apparatuses are provided for driving a modem. A Channel Impulse Response (CIR) is computed through channel estimation. An estimation time position is estimated by applying a weighted-average method to the CIR. A time offset is measured by comparing the estimation time position with a reference time position. The time offset is compensated for.

Abstract: Methods and apparatuses are provided for driving a modem. A Channel Impulse Response (CIR) is computed through channel estimation. An estimation time position is estimated by applying a weighted-average method to the CIR. A time offset is measured by comparing the estimation time position with a reference time position. The time offset is compensated for.

Abstract: A Wireless Local Area Network (WLAN) system and method are provided. The WLAN system includes a first station configured to transmit a first Request To Send (RTS) frame through a wireless channel, and a second station configured to determine whether the wireless channel is in a busy state after receiving the first RTS frame, when the wireless channel is in a busy state, transmit a first Clear To Send (CTS) frame, and after a Point Coordination Function Interframe Space (PIFS) time, transmit a second CTS frame corresponding to the first RTS frame.

Abstract: A data request pattern generating device may include a sequence detector configured to generate data request sequence information based on a plurality of data request signals. The data request signals may be output from a plurality of function blocks. The device may include a time detector configured to generate data request time information based on the data request signals. The device may include a pattern generator configured to generate a data request pattern based on the data request sequence information and the data request time information.

Abstract: An apparatus for and a method of detecting a wobble signal in accordance with a time shift includes comparing a basic wobble signal with reference levels to detect pulses representing the time shift in an analog fashion, and digitally determining a code value for the basic wobble signal on the basis of the widths of the pulses using a channel clock signal and a wobble clock signal. The determined code value is accumulated and serves as a basis on which final wobble data is produced.

Abstract: An automatic gain controller includes a voltage control gain amplifier amplifying input signals in response to a control voltage and producing output signals. A level detector detects peak and bottom levels of the output signals of the voltage control gain amplifier, and an analog-digital converter (ADC) converts the detected peak and bottom levels into digital signals. A peak detector detects a digital peak in response to a difference between the digital peak level and digital bottom level, and a voltage controller compares the digital peak and a reference voltage, and controls the control voltage.

Abstract: An apparatus and method for digitally detecting a tracking error signal using multiple phase clocks. The apparatus includes a phase extractor receiving four divided outputs in response to light reflected from an optical disk and extracting four divided phases, respectively, a phase difference detector detecting phase differences between two phases among the four divided phases, a multiple phase clock generator generating a plurality of phase clocks in response to a predetermined clock signal, a phase error detector counting phase differences in response to each of the plurality of phase clocks, summing the counted phase differences, and detecting a phase error, and a tracking error output unit detecting the tracking error signal in response to the phase error and outputting the detected tracking error signal.

Abstract: A focus layer jump control circuit may include a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal; a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal; a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal; an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; and an output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.

Abstract: An apparatus for processing a defect includes a defect detection unit and a main filter. The defect detection unit detects a presence of a defect in a disc, and when the defect is detected, outputs a reset signal to the main filter. The main filter receives a focus error signal or a tracking error signal, which are digital signals, and outputs a focus regulation signal or a tracking regulation signal to regulate a focus or a tracking location of the disc by filtering the focus error signal or the tracking error signal. The reset signal is applied to the main filter and resets the signal values of a high-frequency component existing in the main filter to 0. Using the apparatus, a peaking phenomenon of the focus regulation signal or the tracking regulation signal can be removed and, accordingly, an accurate servo filter characteristic can be obtained.

Abstract: An analog level meter and a method of measuring an analog signal level may be provided. The analog level meter may include a comparator, a duty counter, an analog level detector and/or a digital to analog converter (DAC). The comparator may compare a voltage level of the analog signal with a reference voltage and generate an up-down signal. The duty counter may count a duty value of the up-down signal. The analog level detector may output a duty error value obtained by subtracting a target duty value from the duty value of the up-down signal. The analog level meter may output the reference voltage as a measured value of the analog signal when the duty error value is a desired or predetermined value.

Abstract: A focus layer jump control circuit may include a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal; a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal; a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal; an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; and an output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.