Patents by Inventor Junho J. H. Cho

Junho J. H. Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bias compensation method and system for minimizing process, voltage and temperature corner variations
    Patent number: 8604826
    Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 10, 2013
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Junho J. H. Cho, Chihou C. L. Lee
  • BIAS COMPENSATION METHOD AND SYSTEM FOR MINIMIZING PROCESS, VOLTAGE AND TEMPERATURE CORNER VARIATIONS
    Publication number: 20130154684
    Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicants: ADVANCED MICRO DEVICES, INC.
    Inventors: Junho J.H. Cho, Chihou C.L. Lee
  • Real time averaged impedance calibration for on-die termination
    Patent number: 8384424
    Abstract: An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: February 26, 2013
    Assignee: ATI Technologies ULC
    Inventor: Junho J. H. Cho
  • REAL TIME AVERAGED IMPEDANCE CALIBRATION FOR ON-DIE TERMINATION
    Publication number: 20120256654
    Abstract: An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 11, 2012
    Inventor: Junho J. H. Cho